From: Marek Olšák <marek.ol...@amd.com>
Cc: 17.1 <mesa-sta...@lists.freedesktop.org>
---
src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
src/gallium/drivers/radeonsi/si_state_shaders.c | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9b7b52c..193187b 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -372,21 +372,22 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
/* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
if (ia_switch_on_eoi)
partial_es_wave = true;
return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ?
wd_switch_on_eop : 0) |
- S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ?
+ /* The following field was moved to VGT_SHADER_STAGES_EN in
GFX9. */
+ S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
max_primgroup_in_wave : 0) |
S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
}
void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
{
for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
for (int multi_instances = 0; multi_instances < 2; multi_instances++)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 21185c3..34cd6d4 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2535,20 +2535,23 @@ static void si_update_vgt_shader_config(struct
si_context *sctx)
S_028B54_GS_EN(1) |
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
else
stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
} else if (sctx->gs_shader.cso) {
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
S_028B54_GS_EN(1) |
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
}
+ if (sctx->b.chip_class >= GFX9)
+ stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
+
si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
}
si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
}
static void si_update_so(struct si_context *sctx, struct si_shader_selector
*shader)
{
struct pipe_stream_output_info *so = &shader->so;
uint32_t enabled_stream_buffers_mask = 0;
int i;
--
2.7.4
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