I wanted to flip things over and use smxx notation...
On Apr 10, 2017 6:20 PM, "Samuel Pitoiset" <samuel.pitoi...@gmail.com>
wrote:
> Not sure why you get confused here. The chipset names are globally
> consistent inside the codegen part and we never use SMxx. Maybe add a
> comment like:
>
> #define NVISA_GK104_CHIPSET 0xe0 /* SM30 */
>
> If you really need this?
>
> On 04/10/2017 11:41 PM, Matthew Mondazzi wrote:
>
>> Define references to chipset did not actually use chipset, leading to
>> confusion. More relevant ISA constants put in place of chipset compares.
>>
>> Signed-off-by: Matthew Mondazzi <msmonda...@gmail.com>
>> ---
>> .../drivers/nouveau/codegen/nv50_ir_driver.h | 7 ++--
>> .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 24 +++++------
>> .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 46
>> +++++++++++-----------
>> .../nouveau/codegen/nv50_ir_target_nvc0.cpp | 6 +--
>> 4 files changed, 42 insertions(+), 41 deletions(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> index e7d840d..76c815e 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> @@ -75,9 +75,10 @@ struct nv50_ir_prog_symbol
>> uint32_t offset;
>> };
>> -#define NVISA_GK104_CHIPSET 0xe0
>> -#define NVISA_GK20A_CHIPSET 0xea
>> -#define NVISA_GM107_CHIPSET 0x110
>> +#define NVISA_SM30 0xe0
>> +#define NVISA_SM35 0xea
>> +#define NVISA_SM50 0x110
>> +
>> struct nv50_ir_prog_info
>> {
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> index 5467447..ed29661 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> @@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
>> void
>> CodeEmitterNVC0::emitMADSP(const Instruction *i)
>> {
>> - assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
>> + assert(targ->getChipset() >= NVISA_SM30);
>> emitForm_A(i, HEX64(00000000, 00000003));
>> @@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
>> case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
>> case FILE_MEMORY_SHARED:
>> if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>> opc = 0xb8000000;
>> else
>> opc = 0xcc000000;
>> @@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
>> code[0] = 0x00000005;
>> code[1] = opc;
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
>> + if (targ->getChipset() >= NVISA_SM30) {
>> // Unlocked store on shared memory can fail.
>> if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
>> i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
>> @@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>> case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
>> case FILE_MEMORY_SHARED:
>> if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>> opc = 0xa8000000;
>> else
>> opc = 0xc4000000;
>> @@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>> code[0] |= 63 << 14;
>> if (p >= 0) {
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>> defId(i->def(p), 8);
>> else
>> defId(i->def(p), 32 + 18);
>> @@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction
>> *i)
>> void
>> CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
>> {
>> - assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> + assert(targ->getChipset() < NVISA_SM30);
>> if (i->tex.rIndirectSrc < 0) {
>> code[1] |= 0x00004000;
>> @@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const TexInstruction
>> *i)
>> void
>> CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
>> {
>> - assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> + assert(targ->getChipset() < NVISA_SM30);
>> code[1] |= (i->tex.target.getDim() - 1) << 12;
>> if (i->tex.target.isArray() || i->tex.target.isCube() ||
>> @@ -2390,7 +2390,7 @@ CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
>> void
>> CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
>> {
>> - assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> + assert(targ->getChipset() < NVISA_SM30);
>> code[0] = 0x5;
>> code[1] = 0xf0000000;
>> @@ -2413,7 +2413,7 @@ CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
>> void
>> CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
>> {
>> - assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> + assert(targ->getChipset() < NVISA_SM30);
>> code[0] = 0x5;
>> code[1] = 0xd4000000 | (i->subOp << 15);
>> @@ -2431,7 +2431,7 @@ CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
>> void
>> CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
>> {
>> - assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> + assert(targ->getChipset() < NVISA_SM30);
>> code[0] = 0x5;
>> code[1] = 0xdc000000 | (i->subOp << 15);
>> @@ -2751,14 +2751,14 @@ CodeEmitterNVC0::emitInstruction(Instruction
>> *insn)
>> emitMADSP(insn);
>> break;
>> case OP_SULDB:
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>> emitSULDGB(insn->asTex());
>> else
>> emitSULDB(insn->asTex());
>> break;
>> case OP_SUSTB:
>> case OP_SUSTP:
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>> emitSUSTGx(insn->asTex());
>> else
>> emitSUSTx(insn->asTex());
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> index 732e1a9..a887436 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -129,11 +129,11 @@ NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
>> // SM30+ stores the indirect handle as a separate arg, which comes
>> before
>> // the LOD.
>> - if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET &&
>> + if (prog->getTarget()->getChipset() >= NVISA_SM30 &&
>> i->tex.rIndirectSrc >= 0)
>> arg++;
>> // SM20 stores indirect handle combined with array coordinate
>> - if (prog->getTarget()->getChipset() < NVISA_GK104_CHIPSET &&
>> + if (prog->getTarget()->getChipset() < NVISA_SM30 &&
>> !i->tex.target.isArray() &&
>> i->tex.rIndirectSrc >= 0)
>> arg++;
>> @@ -162,7 +162,7 @@ NVC0LegalizeSSA::handleShift(Instruction *lo)
>> // SM30 and prior don't have the fancy new SHF.L/R ops. So the logic
>> has to
>> // be completely emulated. For SM35+, we can use the more directed
>> SHF
>> // operations.
>> - if (prog->getTarget()->getChipset() < NVISA_GK20A_CHIPSET) {
>> + if (prog->getTarget()->getChipset() < NVISA_SM35) {
>> // The strategy here is to handle shifts >= 32 and less than 32 as
>> // separate parts.
>> //
>> @@ -629,7 +629,7 @@ NVC0LegalizePostRA::visit(Function *fn)
>> pOne = new_LValue(fn, FILE_PREDICATE);
>> carry = new_LValue(fn, FILE_FLAGS);
>> - rZero->reg.data.id = (prog->getTarget()->getChipset() >=
>> NVISA_GK20A_CHIPSET) ? 255 : 63;
>> + rZero->reg.data.id = (prog->getTarget()->getChipset() >= NVISA_SM35)
>> ? 255 : 63;
>> carry->reg.data.id = 0;
>> pOne->reg.data.id = 7;
>> @@ -860,7 +860,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
>> // array + offsets
>> // derivatives
>> - if (chipset >= NVISA_GK104_CHIPSET) {
>> + if (chipset >= NVISA_SM30) {
>> if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
>> // XXX this ignores tsc, and assumes a 1:1 mapping
>> assert(i->tex.rIndirectSrc >= 0);
>> @@ -976,14 +976,14 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
>> // does. Right now we don't know how to pass both in, and this case
>> can't
>> // happen with OpenGL. On nve0, the sample id is part of the texture
>> // coordinate argument.
>> - assert(chipset >= NVISA_GK104_CHIPSET ||
>> + assert(chipset >= NVISA_SM30 ||
>> !i->tex.useOffsets || !i->tex.target.isMS());
>> // offset is between lod and dc
>> if (i->tex.useOffsets) {
>> int n, c;
>> int s = i->srcCount(0xff, true);
>> - if (i->op != OP_TXD || chipset < NVISA_GK104_CHIPSET) {
>> + if (i->op != OP_TXD || chipset < NVISA_SM30) {
>> if (i->tex.target.isShadow())
>> s--;
>> if (i->srcExists(s)) // move potential predicate out of the way
>> @@ -1020,7 +1020,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
>> assert(!"non-immediate offset passed to non-TXG");
>> imm |= (val.reg.data.u32 & 0xf) << (c * 4);
>> }
>> - if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
>> + if (i->op == OP_TXD && chipset >= NVISA_SM30) {
>> // The offset goes into the upper 16 bits of the array
>> index. So
>> // create it if it's not already there, and INSBF it if it
>> already
>> // is.
>> @@ -1041,7 +1041,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
>> }
>> }
>> - if (chipset >= NVISA_GK104_CHIPSET) {
>> + if (chipset >= NVISA_SM30) {
>> //
>> // If TEX requires more than 4 sources, the 2nd register tuple
>> must be
>> // aligned to 4, even if it consists of just a single 4-byte
>> register.
>> @@ -1083,7 +1083,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction
>> *i)
>> // indirect are separate (and both precede the coordinates). Maxwell
>> is
>> // handled in a separate function.
>> unsigned array;
>> - if (targ->getChipset() < NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() < NVISA_SM30)
>> array = i->tex.target.isArray() || i->tex.rIndirectSrc >= 0;
>> else
>> array = i->tex.target.isArray() + (i->tex.rIndirectSrc >= 0);
>> @@ -1152,7 +1152,7 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
>> unsigned expected_args = arg;
>> const int chipset = prog->getTarget()->getChipset();
>> - if (chipset >= NVISA_GK104_CHIPSET) {
>> + if (chipset >= NVISA_SM30) {
>> if (!txd->tex.target.isArray() && txd->tex.useOffsets)
>> expected_args++;
>> if (txd->tex.rIndirectSrc >= 0 || txd->tex.sIndirectSrc >= 0)
>> @@ -1189,7 +1189,7 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
>> // In this case we have fewer than 4 "real" arguments, which means
>> that
>> // handleTEX didn't apply any padding. However we have to make sure
>> that
>> // the second "group" of arguments still gets padded up to 4.
>> - if (chipset >= NVISA_GK104_CHIPSET) {
>> + if (chipset >= NVISA_SM30) {
>> int s = arg + 2 * dim;
>> if (s >= 4 && s < 7) {
>> if (txd->srcExists(s)) // move potential predicate out of the
>> way
>> @@ -1206,7 +1206,7 @@ bool
>> NVC0LoweringPass::handleTXQ(TexInstruction *txq)
>> {
>> const int chipset = prog->getTarget()->getChipset();
>> - if (chipset >= NVISA_GK104_CHIPSET && txq->tex.rIndirectSrc < 0)
>> + if (chipset >= NVISA_SM30 && txq->tex.rIndirectSrc < 0)
>> txq->tex.r += prog->driver->io.texBindBase / 4;
>> if (txq->tex.rIndirectSrc < 0)
>> @@ -1219,7 +1219,7 @@ NVC0LoweringPass::handleTXQ(TexInstruction *txq)
>> assert(ticRel);
>> - if (chipset < NVISA_GK104_CHIPSET) {
>> + if (chipset < NVISA_SM30) {
>> LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
>> txq->setSrc(txq->tex.rIndirectSrc, NULL);
>> @@ -1501,9 +1501,9 @@ NVC0LoweringPass::handleATOM(Instruction *atom)
>> case FILE_MEMORY_SHARED:
>> // For Fermi/Kepler, we have to use ld lock/st unlock to perform
>> atomic
>> // operations on shared memory. For Maxwell, ATOMS is enough.
>> - if (targ->getChipset() < NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() < NVISA_SM30)
>> handleSharedATOM(atom);
>> - else if (targ->getChipset() < NVISA_GM107_CHIPSET)
>> + else if (targ->getChipset() < NVISA_SM50)
>> handleSharedATOMNVE4(atom);
>> return true;
>> default:
>> @@ -1552,7 +1552,7 @@ NVC0LoweringPass::handleATOM(Instruction *atom)
>> bool
>> NVC0LoweringPass::handleCasExch(Instruction *cas, bool needCctl)
>> {
>> - if (targ->getChipset() < NVISA_GM107_CHIPSET) {
>> + if (targ->getChipset() < NVISA_SM50) {
>> if (cas->src(0).getFile() == FILE_MEMORY_SHARED) {
>> // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
>> return false;
>> @@ -2391,7 +2391,7 @@ NVC0LoweringPass::handleLDST(Instruction *i)
>> assert(prog->getType() != Program::TYPE_FRAGMENT); // INTERP
>> }
>> } else if (i->src(0).getFile() == FILE_MEMORY_CONST) {
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET &&
>> + if (targ->getChipset() >= NVISA_SM30 &&
>> prog->getType() == Program::TYPE_COMPUTE) {
>> // The launch descriptor only allows to set up 8 CBs, but
>> OpenGL
>> // requires at least 12 UBOs. To bypass this limitation, we
>> store the
>> @@ -2568,7 +2568,7 @@ NVC0LoweringPass::handleRDSV(Instruction *i)
>> case SV_NTID:
>> case SV_NCTAID:
>> case SV_GRIDID:
>> - assert(targ->getChipset() >= NVISA_GK104_CHIPSET); // mov $sreg
>> otherwise
>> + assert(targ->getChipset() >= NVISA_SM30); // mov $sreg otherwise
>> if (sym->reg.data.sv.index == 3) {
>> i->op = OP_MOV;
>> i->setSrc(0, bld.mkImm(sv == SV_GRIDID ? 0 : 1));
>> @@ -2845,9 +2845,9 @@ NVC0LoweringPass::visit(Instruction *i)
>> case OP_SUSTP:
>> case OP_SUREDB:
>> case OP_SUREDP:
>> - if (targ->getChipset() >= NVISA_GM107_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM50)
>> handleSurfaceOpGM107(i->asTex());
>> - else if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + else if (targ->getChipset() >= NVISA_SM30)
>> handleSurfaceOpNVE4(i->asTex());
>> else
>> handleSurfaceOpNVC0(i->asTex());
>> @@ -2869,13 +2869,13 @@ NVC0LoweringPass::visit(Instruction *i)
>> * interpolation ops in frag shaders.
>> */
>> bool doAfetch = false;
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET &&
>> + if (targ->getChipset() >= NVISA_SM30 &&
>> !i->perPatch &&
>> (i->op == OP_VFETCH || i->op == OP_EXPORT) &&
>> i->src(0).isIndirect(0)) {
>> doAfetch = true;
>> }
>> - if (targ->getChipset() >= NVISA_GM107_CHIPSET &&
>> + if (targ->getChipset() >= NVISA_SM50 &&
>> (i->op == OP_LINTERP || i->op == OP_PINTERP) &&
>> i->src(0).isIndirect(0)) {
>> doAfetch = true;
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
>> index 0df528f..62c3740 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
>> @@ -279,7 +279,7 @@ TargetNVC0::getSVAddress(DataFile shaderFile, const
>> Symbol *sym) const
>> const SVSemantic sv = sym->reg.data.sv.sv;
>> const bool isInput = shaderFile == FILE_SHADER_INPUT;
>> - const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
>> + const bool kepler = getChipset() >= NVISA_SM30;
>> switch (sv) {
>> case SV_POSITION: return 0x070 + idx * 4;
>> @@ -407,10 +407,10 @@ TargetNVC0::isAccessSupported(DataFile file,
>> DataType ty) const
>> if (ty == TYPE_NONE)
>> return false;
>> if (file == FILE_MEMORY_CONST) {
>> - if (getChipset() >= NVISA_GM107_CHIPSET)
>> + if (getChipset() >= NVISA_SM50)
>> return typeSizeof(ty) <= 4;
>> else
>> - if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?
>> + if (getChipset() >= NVISA_SM30) // wrong encoding ?
>> return typeSizeof(ty) <= 8;
>> }
>> if (ty == TYPE_B96)
>>
>> _______________________________________________
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> mesa-dev@lists.freedesktop.org
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>
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