From: Dave Airlie <airl...@redhat.com>
This fixes an old bug that seems to get triggered by
dEQP-VK.memory.requirements.image.sparse_tiling_optimal
We return early when allocating S8_UINT due to there being
no color or depth, and end up with image size of 0.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 48 ++++++++++++----------
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index 0433952..53ca6ff 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -481,28 +481,32 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
surf->htile_size = surf->htile_slice_size = 0;
surf->htile_alignment = 1;
- /* Calculate texture layout information. */
- for (level = 0; level <= surf->last_level; level++) {
- r = radv_compute_level(ws->addrlib, surf, false, level, type,
compressed,
- &AddrSurfInfoIn, &AddrSurfInfoOut,
&AddrDccIn, &AddrDccOut);
- if (r)
- return r;
-
- if (level == 0) {
- surf->bo_alignment = AddrSurfInfoOut.baseAlign;
- surf->pipe_config =
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
- radv_set_micro_tile_mode(surf, &ws->info);
-
- /* For 2D modes only. */
- if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1)
{
- surf->bankw =
AddrSurfInfoOut.pTileInfo->bankWidth;
- surf->bankh =
AddrSurfInfoOut.pTileInfo->bankHeight;
- surf->mtilea =
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
- surf->tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
- surf->num_banks =
AddrSurfInfoOut.pTileInfo->banks;
- surf->macro_tile_index =
AddrSurfInfoOut.macroModeIndex;
- } else {
- surf->macro_tile_index = 0;
+ if (AddrSurfInfoIn.flags.color || AddrSurfInfoIn.flags.depth) {
+ /* Calculate texture layout information. */
+ for (level = 0; level <= surf->last_level; level++) {
+ r = radv_compute_level(ws->addrlib, surf, false, level,
type, compressed,
+ &AddrSurfInfoIn,
&AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
+ if (r) {
+ assert(0);
+ return r;
+ }
+
+ if (level == 0) {
+ surf->bo_alignment = AddrSurfInfoOut.baseAlign;
+ surf->pipe_config =
AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
+ radv_set_micro_tile_mode(surf, &ws->info);
+
+ /* For 2D modes only. */
+ if (AddrSurfInfoOut.tileMode >=
ADDR_TM_2D_TILED_THIN1) {
+ surf->bankw =
AddrSurfInfoOut.pTileInfo->bankWidth;
+ surf->bankh =
AddrSurfInfoOut.pTileInfo->bankHeight;
+ surf->mtilea =
AddrSurfInfoOut.pTileInfo->macroAspectRatio;
+ surf->tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
+ surf->num_banks =
AddrSurfInfoOut.pTileInfo->banks;
+ surf->macro_tile_index =
AddrSurfInfoOut.macroModeIndex;
+ } else {
+ surf->macro_tile_index = 0;
+ }
}
}
}
--
2.9.3
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