[Mesa-dev] [PATCH 09/25] radv/ac: setup tess rings on compiler side.

[Dave Airlie]

From: Dave Airlie <airl...@redhat.com>

This just sets up the necessary pointers on the compiler
side for the rings needed for tessellation.

Signed-off-by: Dave Airlie <airl...@redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 13 ++++++++++++-
 src/amd/common/ac_nir_to_llvm.h |  2 ++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 97f6972..984f2c7 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -92,6 +92,8 @@ struct nir_to_llvm_context {
 
        LLVMValueRef esgs_ring;
        LLVMValueRef gsvs_ring;
+       LLVMValueRef hs_ring_tess_offchip;
+       LLVMValueRef hs_ring_tess_factor;
 
        LLVMValueRef prim_mask;
        LLVMValueRef sample_positions;
@@ -432,6 +434,8 @@ static void create_function(struct nir_to_llvm_context *ctx)
        /* until we sort out scratch/global buffers always assign ring offsets 
for gs/vs/es */
        if (ctx->stage == MESA_SHADER_GEOMETRY ||
            ctx->stage == MESA_SHADER_VERTEX ||
+           ctx->stage == MESA_SHADER_TESS_CTRL ||
+           ctx->stage == MESA_SHADER_TESS_EVAL ||
            ctx->is_gs_copy_shader)
                need_ring_offsets = true;
 
@@ -4763,7 +4767,8 @@ static void ac_llvm_finalize_module(struct 
nir_to_llvm_context * ctx)
 static void
 ac_setup_rings(struct nir_to_llvm_context *ctx)
 {
-       if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
+       if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
+           (ctx->stage == MESA_SHADER_TESS_EVAL && 
ctx->options->key.tes.as_es)) {
                ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, 
ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
        }
 
@@ -4784,6 +4789,12 @@ ac_setup_rings(struct nir_to_llvm_context *ctx)
 
                ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, 
ctx->v16i8, "");
        }
+
+       if (ctx->stage == MESA_SHADER_TESS_CTRL ||
+           ctx->stage == MESA_SHADER_TESS_EVAL) {
+               ctx->hs_ring_tess_offchip = 
ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 
RING_HS_TESS_OFFCHIP, false));
+               ctx->hs_ring_tess_factor = 
ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 
RING_HS_TESS_FACTOR, false));
+       }
 }
 
 static
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 82e8ae1..c468d93 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -107,6 +107,8 @@ enum ac_ud_index {
 #define RING_ESGS_GS 2
 #define RING_GSVS_VS 3
 #define RING_GSVS_GS 4
+#define RING_HS_TESS_FACTOR 5
+#define RING_HS_TESS_OFFCHIP 6
 
 // Match MAX_SETS from radv_descriptor_set.h
 #define AC_UD_MAX_SETS MAX_SETS
-- 
2.9.3

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