[Mesa-dev] [PATCH 5/6] radeonsi: emit TGSI_OPCODE_CLOCK

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haeh...@amd.com>

---
 src/gallium/drivers/radeonsi/si_shader.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 46c7d41..415d13b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3150,20 +3150,39 @@ static void membar_emit(
                     TGSI_MEMBAR_SHADER_IMAGE))
                waitcnt &= VM_CNT;
 
        if (flags & TGSI_MEMBAR_SHARED)
                waitcnt &= LGKM_CNT;
 
        if (waitcnt != NOOP_WAITCNT)
                emit_waitcnt(ctx, waitcnt);
 }
 
+static void clock_emit(
+               const struct lp_build_tgsi_action *action,
+               struct lp_build_tgsi_context *bld_base,
+               struct lp_build_emit_data *emit_data)
+{
+       struct si_shader_context *ctx = si_shader_context(bld_base);
+       struct gallivm_state *gallivm = &ctx->gallivm;
+       LLVMValueRef tmp;
+
+       tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
+                                ctx->i64, NULL, 0, 0);
+       tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
+
+       emit_data->output[0] =
+               LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
+       emit_data->output[1] =
+               LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
+}
+
 static LLVMValueRef
 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
                         const struct tgsi_full_src_register *reg)
 {
        LLVMValueRef index;
        LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
                                             SI_PARAM_SHADER_BUFFERS);
 
        if (!reg->Register.Indirect)
                index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
@@ -6475,20 +6494,22 @@ static void si_init_shader_ctx(struct si_shader_context 
*ctx,
        bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
        bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
        bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
        bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
        bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
        bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
        bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
 
        bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
 
+       bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
+
        bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
        bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
        bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
        bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
 
        bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
        bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
        bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
 }
 
-- 
2.9.3

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