[Mesa-dev] [PATCH] radv: Assert when setting 0 registers in a sequence.

[Bas Nieuwenhuizen]

To catch more of those hangs early.

Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
---
 src/amd/vulkan/radv_cs.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 2c8935f3065..8fcdad9dbbd 100644
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -43,6 +43,7 @@ static inline void radeon_set_config_reg_seq(struct 
radeon_winsys_cs *cs, unsign
 {
         assert(reg < R600_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
+       assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
         radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
 }
@@ -57,6 +58,7 @@ static inline void radeon_set_context_reg_seq(struct 
radeon_winsys_cs *cs, unsig
 {
         assert(reg >= R600_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
+       assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
 }
@@ -83,6 +85,7 @@ static inline void radeon_set_sh_reg_seq(struct 
radeon_winsys_cs *cs, unsigned r
 {
        assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
        assert(cs->cdw + 2 + num <= cs->max_dw);
+       assert(num);
        radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
        radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 }
@@ -97,6 +100,7 @@ static inline void radeon_set_uconfig_reg_seq(struct 
radeon_winsys_cs *cs, unsig
 {
        assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
        assert(cs->cdw + 2 + num <= cs->max_dw);
+       assert(num);
        radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
        radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 }
-- 
2.12.1

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