[Mesa-dev] [PATCH 078/140] radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

The registers don't exist on GFX9.
---
 src/gallium/drivers/radeonsi/si_state.c | 34 ++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 6d0a84c..4cd0494 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4073,38 +4073,42 @@ static void si_init_config(struct si_context *sctx)
                raster_config = 0x00000000; /* 0x00000002 */
                raster_config_1 = 0x00000000;
                break;
        case CHIP_KABINI:
        case CHIP_MULLINS:
        case CHIP_STONEY:
                raster_config = 0x00000000;
                raster_config_1 = 0x00000000;
                break;
        default:
-               fprintf(stderr,
-                       "radeonsi: Unknown GPU, using 0 for raster_config\n");
-               raster_config = 0x00000000;
-               raster_config_1 = 0x00000000;
+               if (sctx->b.chip_class <= VI) {
+                       fprintf(stderr,
+                               "radeonsi: Unknown GPU, using 0 for 
raster_config\n");
+                       raster_config = 0x00000000;
+                       raster_config_1 = 0x00000000;
+               }
                break;
        }
 
-       /* Always use the default config when all backends are enabled
-        * (or when we failed to determine the enabled backends).
-        */
-       if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
-               si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
-                              raster_config);
-               if (sctx->b.chip_class >= CIK)
-                       si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
-                                      raster_config_1);
-       } else {
-               si_write_harvested_raster_configs(sctx, pm4, raster_config, 
raster_config_1);
+       if (sctx->b.chip_class <= VI) {
+               if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
+                       /* Always use the default config when all backends are 
enabled
+                        * (or when we failed to determine the enabled 
backends).
+                        */
+                       si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
+                                      raster_config);
+                       if (sctx->b.chip_class >= CIK)
+                               si_pm4_set_reg(pm4, 
R_028354_PA_SC_RASTER_CONFIG_1,
+                                              raster_config_1);
+               } else {
+                       si_write_harvested_raster_configs(sctx, pm4, 
raster_config, raster_config_1);
+               }
        }
 
        si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, 
S_028204_WINDOW_OFFSET_DISABLE(1));
        si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, 
S_028240_WINDOW_OFFSET_DISABLE(1));
        si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
                       S_028244_BR_X(16384) | S_028244_BR_Y(16384));
        si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
        si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
                       S_028034_BR_X(16384) | S_028034_BR_Y(16384));
 
-- 
2.7.4

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