From: Nicolai Hähnle <nicolai.haeh...@amd.com>
Signed-off-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/amd/addrlib/core/addrcommon.h | 2 +-
src/amd/addrlib/core/addrelemlib.cpp | 22 +++++++++++-----------
src/amd/addrlib/core/addrelemlib.h | 2 +-
src/amd/addrlib/core/addrlib.cpp | 2 +-
src/amd/addrlib/core/addrlib.h | 31 +++++++++++++------------------
src/amd/addrlib/core/addrlib1.cpp | 17 ++++++++---------
src/amd/addrlib/core/addrlib1.h | 2 +-
src/amd/addrlib/core/addrobject.cpp | 2 +-
src/amd/addrlib/core/addrobject.h | 2 +-
src/amd/addrlib/r800/ciaddrlib.cpp | 14 +++++++-------
src/amd/addrlib/r800/ciaddrlib.h | 2 +-
src/amd/addrlib/r800/egbaddrlib.cpp | 15 ++++++++-------
src/amd/addrlib/r800/siaddrlib.cpp | 28 ++++++++++++++--------------
13 files changed, 68 insertions(+), 73 deletions(-)
diff --git a/src/amd/addrlib/core/addrcommon.h
b/src/amd/addrlib/core/addrcommon.h
index 9b0cc6d..caed63f 100644
--- a/src/amd/addrlib/core/addrcommon.h
+++ b/src/amd/addrlib/core/addrcommon.h
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addrcommon.h
-* @brief Contains the helper function and constants
+* @brief Contains the helper function and constants.
****************************************************************************************************
*/
#ifndef __ADDR_COMMON_H__
#define __ADDR_COMMON_H__
#include "addrinterface.h"
// ADDR_LNX_KERNEL_BUILD is for internal build
diff --git a/src/amd/addrlib/core/addrelemlib.cpp
b/src/amd/addrlib/core/addrelemlib.cpp
index b894f49..c9d2074 100644
--- a/src/amd/addrlib/core/addrelemlib.cpp
+++ b/src/amd/addrlib/core/addrelemlib.cpp
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addrelemlib.cpp
-* @brief Contains the class implementation for element/pixel related functions
+* @brief Contains the class implementation for element/pixel related functions.
****************************************************************************************************
*/
#include "addrelemlib.h"
#include "addrlib.h"
namespace Addr
{
/**
@@ -713,21 +713,21 @@ VOID ElemLib::GetCompType(
* @brief
* Get components swapped for color surface
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID ElemLib::GetCompSwap(
AddrSurfaceSwap swap, ///< [in] swap mode
- PixelFormatInfo* pInfo) ///< [in/out] output per component info
+ PixelFormatInfo* pInfo) ///< [in,out] output per component info
{
switch (pInfo->comps)
{
case 4:
switch (swap)
{
case ADDR_SWAP_ALT:
SwapComps( 0, 2, pInfo );
break; // BGRA
case ADDR_SWAP_STD_REV:
@@ -804,21 +804,21 @@ VOID ElemLib::GetCompSwap(
* Get components swapped for color surface
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID ElemLib::SwapComps(
UINT_32 c0, ///< [in] component index 0
UINT_32 c1, ///< [in] component index 1
- PixelFormatInfo* pInfo) ///< [in/out] output per component info
+ PixelFormatInfo* pInfo) ///< [in,out] output per component info
{
UINT_32 start;
UINT_32 bits;
start = pInfo->compStart[c0];
pInfo->compStart[c0] = pInfo->compStart[c1];
pInfo->compStart[c1] = start;
bits = pInfo->compBit[c0];
pInfo->compBit[c0] = pInfo->compBit[c1];
@@ -1120,24 +1120,24 @@ BOOL_32 ElemLib::PixGetExportNorm(
* Adjust bpp/base pitch/width/height according to elemMode and expandX/Y
*
* @return
* N/A
****************************************************************************************************
*/
VOID ElemLib::AdjustSurfaceInfo(
ElemMode elemMode, ///< [in] element mode
UINT_32 expandX, ///< [in] decompression expansion factor
in X
UINT_32 expandY, ///< [in] decompression expansion factor
in Y
- UINT_32* pBpp, ///< [in/out] bpp
- UINT_32* pBasePitch, ///< [in/out] base pitch
- UINT_32* pWidth, ///< [in/out] width
- UINT_32* pHeight) ///< [in/out] height
+ UINT_32* pBpp, ///< [in,out] bpp
+ UINT_32* pBasePitch, ///< [in,out] base pitch
+ UINT_32* pWidth, ///< [in,out] width
+ UINT_32* pHeight) ///< [in,out] height
{
UINT_32 packedBits;
UINT_32 basePitch;
UINT_32 width;
UINT_32 height;
UINT_32 bpp;
BOOL_32 bBCnFormat = FALSE;
ADDR_ASSERT(pBpp != NULL);
ADDR_ASSERT(pWidth != NULL && pHeight != NULL && pBasePitch != NULL);
@@ -1245,23 +1245,23 @@ VOID ElemLib::AdjustSurfaceInfo(
* Reverse operation of AdjustSurfaceInfo
*
* @return
* N/A
****************************************************************************************************
*/
VOID ElemLib::RestoreSurfaceInfo(
ElemMode elemMode, ///< [in] element mode
UINT_32 expandX, ///< [in] decompression expansion factor
in X
UINT_32 expandY, ///< [out] decompression expansion factor
in Y
- UINT_32* pBpp, ///< [in/out] bpp
- UINT_32* pWidth, ///< [in/out] width
- UINT_32* pHeight) ///< [in/out] height
+ UINT_32* pBpp, ///< [in,out] bpp
+ UINT_32* pWidth, ///< [in,out] width
+ UINT_32* pHeight) ///< [in,out] height
{
UINT_32 originalBits;
UINT_32 width;
UINT_32 height;
UINT_32 bpp;
ADDR_ASSERT(pBpp != NULL);
ADDR_ASSERT(pWidth != NULL && pHeight != NULL);
if (pBpp)
@@ -1554,21 +1554,21 @@ VOID ElemLib::GetCompBits(
*
* @note
* If clearColor is zero, a default clear value is used in place of
comps[4].
* If float32 is set, full precision is used, else the mantissa is
reduced to 12-bits
*
* @return
* N/A
****************************************************************************************************
*/
VOID ElemLib::SetClearComps(
- ADDR_FLT_32 comps[4], ///< [in/out] components
+ ADDR_FLT_32 comps[4], ///< [in,out] components
BOOL_32 clearColor, ///< [in] TRUE if clear color is set (CLEAR_COLOR)
BOOL_32 float32) ///< [in] TRUE if float32 component (BLEND_FLOAT32)
{
INT_32 i;
// Use default clearvalues if clearColor is disabled
if (clearColor == FALSE)
{
for (i=0; i<3; i++)
{
diff --git a/src/amd/addrlib/core/addrelemlib.h
b/src/amd/addrlib/core/addrelemlib.h
index 2875026..c95c9d6 100644
--- a/src/amd/addrlib/core/addrelemlib.h
+++ b/src/amd/addrlib/core/addrelemlib.h
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addrelemlib.h
-* @brief Contains the class for element/pixel related functions
+* @brief Contains the class for element/pixel related functions.
****************************************************************************************************
*/
#ifndef __ELEM_LIB_H__
#define __ELEM_LIB_H__
#include "addrinterface.h"
#include "addrobject.h"
#include "addrcommon.h"
diff --git a/src/amd/addrlib/core/addrlib.cpp b/src/amd/addrlib/core/addrlib.cpp
index 8553ca6..d4b31e6 100644
--- a/src/amd/addrlib/core/addrlib.cpp
+++ b/src/amd/addrlib/core/addrlib.cpp
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addrlib.cpp
-* @brief Contains the implementation for the AddrLib base class..
+* @brief Contains the implementation for the Addr::Lib class.
****************************************************************************************************
*/
#include "addrinterface.h"
#include "addrlib.h"
#include "addrcommon.h"
#if defined(__APPLE__)
UINT_32 div64_32(UINT_64 n, UINT_32 base)
diff --git a/src/amd/addrlib/core/addrlib.h b/src/amd/addrlib/core/addrlib.h
index 10d029f..e5d4c57 100644
--- a/src/amd/addrlib/core/addrlib.h
+++ b/src/amd/addrlib/core/addrlib.h
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addrlib.h
-* @brief Contains the AddrLib base class definition.
+* @brief Contains the Addr::Lib base class definition.
****************************************************************************************************
*/
#ifndef __ADDR_LIB_H__
#define __ADDR_LIB_H__
#include "addrinterface.h"
#include "addrobject.h"
#include "addrelemlib.h"
@@ -49,24 +49,20 @@
#endif
#ifndef CIASICIDGFXENGINE_R800
#define CIASICIDGFXENGINE_R800 0x00000008
#endif
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
-#ifndef CIASICIDGFXENGINE_SEAISLAND
-#define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
-#endif
-
namespace Addr
{
/**
****************************************************************************************************
* @brief Neutral enums that define pipeinterleave
****************************************************************************************************
*/
enum PipeInterleave
{
@@ -220,49 +216,48 @@ private:
Lib(const Lib& a);
// Disallow the assignment operator
Lib& operator=(const Lib& a);
VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
protected:
- LibClass m_class; ///< Store class type (HWL type)
+ LibClass m_class; ///< Store class type (HWL type)
- ChipFamily m_chipFamily; ///< Chip family translated from the
one in atiid.h
+ ChipFamily m_chipFamily; ///< Chip family translated from the one in
atiid.h
- UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
+ UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
- UINT_32 m_version; ///< Current version
+ UINT_32 m_version; ///< Current version
//
// Global parameters
//
- ConfigFlags m_configFlags; ///< Global configuration flags.
Note this is setup by
+ ConfigFlags m_configFlags; ///< Global configuration flags. Note
this is setup by
/// AddrLib instead of Client except
forceLinearAligned
- UINT_32 m_pipes; ///< Number of pipes
- UINT_32 m_banks; ///< Number of banks
+ UINT_32 m_pipes; ///< Number of pipes
+ UINT_32 m_banks; ///< Number of banks
/// For r800 this is
MC_ARB_RAMCFG.NOOFBANK
/// Keep it here to do default
parameter calculation
- UINT_32 m_pipeInterleaveBytes;
+ UINT_32 m_pipeInterleaveBytes;
///< Specifies the size of contiguous
address space
/// within each tiling pipe when
making linear
/// accesses. (Formerly Group Size)
- UINT_32 m_rowSize; ///< DRAM row size, in bytes
+ UINT_32 m_rowSize; ///< DRAM row size, in bytes
- UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in
pixels
- UINT_32 m_maxSamples; ///< Max numSamples
+ UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
+ UINT_32 m_maxSamples; ///< Max numSamples
private:
- ElemLib* m_pElemLib; ///< Element Lib pointer
+ ElemLib* m_pElemLib; ///< Element Lib pointer
};
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
} // Addr
#endif
-
diff --git a/src/amd/addrlib/core/addrlib1.cpp
b/src/amd/addrlib/core/addrlib1.cpp
index e7ac385..f0cd58c 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addr1lib.cpp
-* @brief Contains the implementation for the AddrLib1 base class..
+* @brief Contains the implementation for the Addr::V1::Lib base class.
****************************************************************************************************
*/
#include "addrinterface.h"
#include "addrlib1.h"
#include "addrcommon.h"
namespace Addr
{
namespace V1
@@ -1699,21 +1699,20 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskCoordFromAddr(
pIn->pTileInfo,
&pOut->x,
&pOut->y,
&pOut->slice);
}
}
return returnCode;
}
-
/**
****************************************************************************************************
* Lib::ComputeTileDataWidthAndHeight
*
* @brief
* Compute the squared cache shape for per-tile data (CMASK and HTILE)
*
* @return
* N/A
*
@@ -3218,28 +3217,28 @@ VOID Lib::AdjustPitchAlignment(
* @return
* N/A
*
****************************************************************************************************
*/
VOID Lib::PadDimensions(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value
1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
- UINT_32* pPitch, ///< [in/out] pitch in pixels
+ UINT_32* pPitch, ///< [in,out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pHeight, ///< [in/out] height in pixels
+ UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
- UINT_32* pSlices, ///< [in/out] number of slices
+ UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
UINT_32 thickness = Thickness(tileMode);
ADDR_ASSERT(padDims <= 3);
//
// Override padding for mip levels
//
@@ -3480,21 +3479,21 @@ BOOL_32 Lib::IsPrtTileMode(
****************************************************************************************************
* Lib::ComputeMipLevel
*
* @brief
* Compute mipmap level width/height/slices
* @return
* N/A
****************************************************************************************************
*/
VOID Lib::ComputeMipLevel(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
) const
{
if (ElemLib::IsBlockCompressed(pIn->format))
{
if (pIn->mipLevel == 0)
{
// DXTn's level 0 must be multiple of 4
// But there are exceptions:
// 1. Internal surface creation in hostblt/vsblt/etc...
// 2. Runtime doesn't reject ATI1/ATI2 whose width/height are not
multiple of 4
@@ -3649,21 +3648,21 @@ AddrTileMode Lib::DegradeLargeThickTile(
/**
****************************************************************************************************
* Lib::PostComputeMipLevel
* @brief
* Compute MipLevel info (including level 0) after surface adjustment
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::PostComputeMipLevel(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in/out] Input structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in,out] Input structure
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output structure
) const
{
// Mipmap including level 0 must be pow2 padded since either SI hw expects
so or it is
// required by CFX for Hw Compatibility between NI and SI. Otherwise it
is only needed for
// mipLevel > 0. Any h/w has different requirement should implement its
own virtual function
if (pIn->flags.pow2Pad)
{
pIn->width = NextPow2(pIn->width);
@@ -3730,21 +3729,21 @@ UINT_32 Lib::HwlGetPipes(
****************************************************************************************************
* Lib::ComputeQbStereoInfo
*
* @brief
* Get quad buffer stereo information
* @return
* TRUE if no error
****************************************************************************************************
*/
BOOL_32 Lib::ComputeQbStereoInfo(
- ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in/out] updated
pOut+pStereoInfo
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] updated
pOut+pStereoInfo
) const
{
BOOL_32 success = FALSE;
if (pOut->pStereoInfo)
{
ADDR_ASSERT(pOut->bpp >= 8);
ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
// Save original height
diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h
index 7c19d10..9c66f53 100644
--- a/src/amd/addrlib/core/addrlib1.h
+++ b/src/amd/addrlib/core/addrlib1.h
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file addrlib1.h
-* @brief Contains the Lib base class definition.
+* @brief Contains the Addr::V1::Lib class definition.
****************************************************************************************************
*/
#ifndef __ADDR_LIB1_H__
#define __ADDR_LIB1_H__
#include "addrlib.h"
namespace Addr
{
diff --git a/src/amd/addrlib/core/addrobject.cpp
b/src/amd/addrlib/core/addrobject.cpp
index 0c5f81a..cb62aa0 100644
--- a/src/amd/addrlib/core/addrobject.cpp
+++ b/src/amd/addrlib/core/addrobject.cpp
@@ -19,21 +19,21 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
-* @file Object.cpp
+* @file addrobject.cpp
* @brief Contains the Object base class implementation.
****************************************************************************************************
*/
#include "addrinterface.h"
#include "addrobject.h"
namespace Addr
{
diff --git a/src/amd/addrlib/core/addrobject.h
b/src/amd/addrlib/core/addrobject.h
index c648386..031103b 100644
--- a/src/amd/addrlib/core/addrobject.h
+++ b/src/amd/addrlib/core/addrobject.h
@@ -19,21 +19,21 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
-* @file Object.h
+* @file addrobject.h
* @brief Contains the Object base class definition.
****************************************************************************************************
*/
#ifndef __ADDR_OBJECT_H__
#define __ADDR_OBJECT_H__
#include "addrtypes.h"
#include "addrcommon.h"
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp
b/src/amd/addrlib/r800/ciaddrlib.cpp
index 839a268..3c0607e 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -854,40 +854,40 @@ VOID CiLib::HwlFmaskPostThunkSurfInfo(
* @brief
* Degrades valid tile mode for thick modes if needed
*
* @return
* Suitable tile mode
****************************************************************************************************
*/
AddrTileMode CiLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
- UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per
slice
+ UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per
slice
) const
{
return baseTileMode;
}
/**
****************************************************************************************************
* CiLib::HwlOverrideTileMode
*
* @brief
* Override THICK to THIN, for specific formats on CI
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlOverrideTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output
structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output
structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
AddrTileType tileType = pInOut->tileType;
// currently, all CI/VI family do not
// support ADDR_TM_PRT_2D_TILED_THICK,ADDR_TM_PRT_3D_TILED_THICK and
// ADDR_TM_PRT_2D_TILED_THIN1, ADDR_TM_PRT_3D_TILED_THIN1
switch (tileMode)
{
@@ -1034,21 +1034,21 @@ VOID CiLib::HwlOverrideTileMode(
*
* @brief
* Select tile modes.
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlSelectTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output
structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output
structure
) const
{
AddrTileMode tileMode;
AddrTileType tileType;
if (pInOut->flags.rotateDisplay)
{
tileMode = ADDR_TM_2D_TILED_THIN1;
tileType = ADDR_ROTATED;
}
@@ -1949,28 +1949,28 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlPadDimensions(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value
1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
- UINT_32* pPitch, ///< [in/out] pitch in pixels
+ UINT_32* pPitch, ///< [in,out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pHeight, ///< [in/out] height in pixels
+ UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
- UINT_32* pSlices, ///< [in/out] number of slices
+ UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
if (m_settings.isVolcanicIslands &&
flags.dccCompatible &&
(numSamples > 1) &&
(mipLevel == 0) &&
IsMacroTiled(tileMode))
{
UINT_32 tileSizePerSample = BITS_TO_BYTES(bpp * MicroTileWidth *
MicroTileHeight);
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 438790a..a9b1607 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -50,21 +50,21 @@ namespace V1
struct CIChipSettings
{
struct
{
UINT_32 isSeaIsland : 1;
UINT_32 isBonaire : 1;
UINT_32 isKaveri : 1;
UINT_32 isSpectre : 1;
UINT_32 isSpooky : 1;
UINT_32 isKalindi : 1;
- // Hawaii is GFXIP 7.2, similar with CI (Bonaire)
+ // Hawaii is GFXIP 7.2
UINT_32 isHawaii : 1;
// VI
UINT_32 isVolcanicIslands : 1;
UINT_32 isIceland : 1;
UINT_32 isTonga : 1;
UINT_32 isFiji : 1;
UINT_32 isPolaris10 : 1;
UINT_32 isPolaris11 : 1;
UINT_32 isPolaris12 : 1;
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp
b/src/amd/addrlib/r800/egbaddrlib.cpp
index 5de3f99..b151682 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file egbaddrlib.cpp
-* @brief Contains the EgBasedLib class implementation
+* @brief Contains the EgBasedLib class implementation.
****************************************************************************************************
*/
#include "egbaddrlib.h"
namespace Addr
{
namespace V1
{
@@ -42,21 +42,22 @@ namespace V1
****************************************************************************************************
* EgBasedLib::EgBasedLib
*
* @brief
* Constructor
*
* @note
*
****************************************************************************************************
*/
-EgBasedLib::EgBasedLib(const Client* pClient) :
+EgBasedLib::EgBasedLib(const Client* pClient)
+ :
Lib(pClient),
m_ranks(0),
m_logicalBanks(0),
m_bankInterleave(1)
{
}
/**
****************************************************************************************************
* EgBasedLib::~EgBasedLib
@@ -736,21 +737,21 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMicroTiled(
* TRUE if no error occurs
****************************************************************************************************
*/
BOOL_32 EgBasedLib::HwlReduceBankWidthHeight(
UINT_32 tileSize, ///< [in] tile size
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
UINT_32 bankHeightAlign, ///< [in] bank height alignment
UINT_32 pipes, ///< [in] pipes
- ADDR_TILEINFO* pTileInfo ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo ///< [in,out] bank structure.
) const
{
UINT_32 macroAspectAlign;
BOOL_32 valid = TRUE;
if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize)
{
BOOL_32 stillGreater = TRUE;
// Try reducing bankWidth first
@@ -839,21 +840,21 @@ BOOL_32 EgBasedLib::HwlReduceBankWidthHeight(
* @return
* TRUE if no error occurs
****************************************************************************************************
*/
BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 mipLevel, ///< [in] mip level
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32* pBaseAlign, ///< [out] base address alignment
in bytes
UINT_32* pPitchAlign, ///< [out] pitch alignment in
pixels
UINT_32* pHeightAlign, ///< [out] height alignment in
pixels
UINT_32* pMacroTileWidth, ///< [out] macro tile width in
pixels
UINT_32* pMacroTileHeight ///< [out] macro tile height in
pixels
) const
{
BOOL_32 valid = SanityCheckMacroTiled(pTileInfo);
if (valid)
@@ -1240,21 +1241,21 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
* @brief
* Degrades valid tile mode for thick modes if needed
*
* @return
* Suitable tile mode
****************************************************************************************************
*/
AddrTileMode EgBasedLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
- UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per
slice
+ UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per
slice
) const
{
ADDR_ASSERT(numSlices < Thickness(baseTileMode));
// if pBytesPerTile is NULL, this is a don't-care....
UINT_32 bytesPerTile = pBytesPerTile != NULL ? *pBytesPerTile : 64;
AddrTileMode expTileMode = baseTileMode;
switch (baseTileMode)
{
case ADDR_TM_1D_TILED_THICK:
@@ -4748,22 +4749,22 @@ UINT_32 EgBasedLib::HwlGetPitchAlignmentMicroTiled(
* Logical slice size in bytes
****************************************************************************************************
*/
UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, ///< [in] thickness
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pPitch, ///< [in/out] pointer to pitch
- UINT_32* pHeight ///< [in/out] pointer to height
+ UINT_32* pPitch, ///< [in,out] pointer to pitch
+ UINT_32* pHeight ///< [in,out] pointer to height
) const
{
UINT_64 logicalSliceSize;
UINT_64 physicalSliceSize;
UINT_32 pitch = *pPitch;
UINT_32 height = *pHeight;
// Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so
actually numSamples == 1)
logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height *
bpp * numSamples);
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp
b/src/amd/addrlib/r800/siaddrlib.cpp
index 9d3f5aa..f1f5a1b 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -1520,23 +1520,23 @@ UINT_32 SiLib::HwlGetPitchAlignmentLinear(
* @return
* Logical slice size in bytes
****************************************************************************************************
*/
UINT_64 SiLib::HwlGetSizeAdjustmentLinear(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pPitch, ///< [in/out] pointer to pitch
- UINT_32* pHeight, ///< [in/out] pointer to height
- UINT_32* pHeightAlign ///< [in/out] pointer to height align
+ UINT_32* pPitch, ///< [in,out] pointer to pitch
+ UINT_32* pHeight, ///< [in,out] pointer to height
+ UINT_32* pHeightAlign ///< [in,out] pointer to height align
) const
{
UINT_64 sliceSize;
if (tileMode == ADDR_TM_LINEAR_GENERAL)
{
sliceSize = BITS_TO_BYTES(static_cast<UINT_64>(*pPitch) * (*pHeight) *
bpp * numSamples);
}
else
{
UINT_32 pitch = *pPitch;
@@ -1675,22 +1675,22 @@ UINT_32 SiLib::HwlGetPitchAlignmentMicroTiled(
* Logical slice size in bytes
****************************************************************************************************
*/
UINT_64 SiLib::HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, ///< [in] thickness
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pPitch, ///< [in/out] pointer to pitch
- UINT_32* pHeight ///< [in/out] pointer to height
+ UINT_32* pPitch, ///< [in,out] pointer to pitch
+ UINT_32* pHeight ///< [in,out] pointer to height
) const
{
UINT_64 logicalSliceSize;
UINT_64 physicalSliceSize;
UINT_32 pitch = *pPitch;
UINT_32 height = *pHeight;
// Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so
actually numSamples == 1)
logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height *
bpp * numSamples);
@@ -2309,22 +2309,22 @@ UINT_32 SiLib::HwlComputeXmaskCoordYFrom8Pipe(
* SiLib::HwlComputeSurfaceCoord2DFromBankPipe
*
* @brief
* Compute surface x,y coordinates from bank/pipe info
* @return
* N/A
****************************************************************************************************
*/
VOID SiLib::HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, ///< [in] tile mode
- UINT_32* pX, ///< [in/out] x coordinate
- UINT_32* pY, ///< [in/out] y coordinate
+ UINT_32* pX, ///< [in,out] x coordinate
+ UINT_32* pY, ///< [in,out] y coordinate
UINT_32 slice, ///< [in] slice index
UINT_32 bank, ///< [in] bank number
UINT_32 pipe, ///< [in] pipe number
UINT_32 bankSwizzle,///< [in] bank swizzle
UINT_32 pipeSwizzle,///< [in] pipe swizzle
UINT_32 tileSlices, ///< [in] slices in a micro tile
BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are
ignored
ADDR_TILEINFO* pTileInfo ///< [in] bank structure. **All fields to
be valid on entry**
) const
{
@@ -2548,21 +2548,21 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
/**
****************************************************************************************************
* SiLib::HwlComputeMipLevel
* @brief
* Compute MipLevel info (including level 0)
* @return
* TRUE if HWL's handled
****************************************************************************************************
*/
BOOL_32 SiLib::HwlComputeMipLevel(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
) const
{
// basePitch is calculated from level 0 so we only check this for mipLevel
> 0
if (pIn->mipLevel > 0)
{
// Note: Don't check expand 3x formats(96 bit) as the basePitch is not
pow2 even if
// we explicity set pow2Pad flag. The 3x base pitch is padded to pow2
but after being
// divided by expandX factor (3) - to program texture pitch, the
basePitch is never pow2.
if (ElemLib::IsExpand3x(pIn->format) == FALSE)
{
@@ -2588,21 +2588,21 @@ BOOL_32 SiLib::HwlComputeMipLevel(
* SiLib::HwlCheckLastMacroTiledLvl
*
* @brief
* Sets pOut->last2DLevel to TRUE if it is
* @note
*
****************************************************************************************************
*/
VOID SiLib::HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
- ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in/out] Output structure
(used as input, too)
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Output structure
(used as input, too)
) const
{
// pow2Pad covers all mipmap cases
if (pIn->flags.pow2Pad)
{
ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
UINT_32 nextPitch;
UINT_32 nextHeight;
UINT_32 nextSlices;
@@ -2665,21 +2665,21 @@ VOID SiLib::HwlCheckLastMacroTiledLvl(
* @brief
* Degrades valid tile mode for thick modes if needed
*
* @return
* Suitable tile mode
****************************************************************************************************
*/
AddrTileMode SiLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
- UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per
slice
+ UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per
slice
) const
{
return EgBasedLib::HwlDegradeThickTileMode(baseTileMode, numSlices,
pBytesPerTile);
}
/**
****************************************************************************************************
* SiLib::HwlTileInfoEqual
*
* @brief
@@ -3139,21 +3139,21 @@ UINT_32 SiLib::HwlComputeFmaskBits(
*
* @brief
* Override tile modes (for PRT only, avoid client passes in an invalid
PRT mode for SI.
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID SiLib::HwlOverrideTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input
output structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input
output structure
) const
{
AddrTileMode tileMode = pInOut->tileMode;
switch (tileMode)
{
case ADDR_TM_PRT_TILED_THIN1:
tileMode = ADDR_TM_2D_TILED_THIN1;
break;
@@ -3209,21 +3209,21 @@ VOID SiLib::HwlOverrideTileMode(
*
* @brief
* Select tile modes.
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID SiLib::HwlSelectTileMode(
- ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in/out] input output
structure
+ ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output
structure
) const
{
AddrTileMode tileMode;
AddrTileType tileType;
if (pInOut->flags.volume)
{
if (pInOut->numSlices >= 8)
{
tileMode = ADDR_TM_2D_TILED_XTHICK;
@@ -3501,23 +3501,23 @@ VOID SiLib::InitEquationTable()
* SiLib::IsEquationSupported
*
* @brief
* Check if it is supported for given bpp and tile config to generate a
equation.
*
* @return
* TRUE if supported
****************************************************************************************************
*/
BOOL_32 SiLib::IsEquationSupported(
- UINT_32 bpp, ///< Bits per pixel
+ UINT_32 bpp, ///< Bits per pixel
TileConfig tileConfig, ///< Tile config
- INT_32 tileIndex ///< Tile index
+ INT_32 tileIndex ///< Tile index
) const
{
BOOL_32 supported = TRUE;
// Linear tile mode is not supported in swizzle pattern equation
if (IsLinear(tileConfig.mode))
{
supported = FALSE;
}
// These tile modes are for Tex2DArray and Tex3D which has depth
(num_slice > 1) use,
--
2.7.4
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