Hi, This series implements initial support for Ivybridge FP64 for both align16 and align1 backends, and with that we can enable FP64 and OpenGL 4.0 in Ivybridge.
These patches are available in our repository for testing. You can clone it using the following command: $ git clone -b i965-fp64-gen7-ivb-scalar-vec4-rc4 \ https://github.com/Igalia/mesa.git This is the fourth version of the patch series. The changes against v3 are: generalization of d2x pass to allow conversions to narrower or equal size types and rename it, fix properly the DF CMP with null destination bug, split VEC4_OPCODE_FROM_DOUBLE opcode into two (one for conversion, another for gathering the spread data). The only feature missing in this series would be register spilling of 64-bit data. With this series all existing FP64 tests in Piglit pass on Ivybridge, except for ~36 tests that fail to spill registers (mostly the same varying-packing tests that failed in the scalar backend before Curro fixed the scalar spilling implementation for SIMD32). Best regards, Sam Francisco Jerez (1): i965/fs: Get 64-bit indirect moves working on IVB. Iago Toral Quiroga (1): i965/disasm: also print nibctrl in IVB for execsize=8 Juan A. Suarez Romero (7): i965/fs: add helper to retrieve instruction data size i965/fs: double regioning parameters and execsize for DF in IVB/BYT i965/fs: fix dst stride in IVB/BYT type conversions i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT i965/vec4: keep original type when dealing with null registers i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT i965/vec4: consider subregister offset in live variables Matt Turner (5): i965: Handle IVB DF differences in the validator. i965: Use <0,2,1> region for scalar DF sources on IVB/BYT. i965: Use source region <1,2,0> when converting to DF. i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT. i965: Use correct VertStride on align16 instructions. Samuel Iglesias Gonsálvez (14): i965/fs: clamp exec_size when an instruction has a scalar DF source i965/fs: generalize the legalization d2x pass i965/fs: rename lower_d2x to lower_narrow_conversions i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT i965/vec4: split DF instructions and later double its execsize in IVB/BYT i965/vec4: split d2x conversion and data gathering from one opcode to two explicit ones i965/vec4: fix assert to detect SIMD lowered DF instructions in IVB i965/vec4: fix SIMD-width lowering for VEC4_OPCODE_FROM_DOUBLE i965/vec4: use vec4_builder to emit instructions in setup_imm_df() i965/vec4: don't do horizontal stride on some register file types i965/vec4/dce: improve track of partial flag register writes i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail i965: enable OpenGL 4.0 to Ivybridge/Baytrail docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+ docs/features.txt | 4 +- src/intel/Makefile.sources | 2 +- src/intel/compiler/brw_disasm.c | 6 +- src/intel/compiler/brw_eu_emit.c | 72 ++++++++++-- src/intel/compiler/brw_eu_validate.c | 24 ++++ src/intel/compiler/brw_fs.cpp | 54 ++++++--- src/intel/compiler/brw_fs.h | 16 ++- src/intel/compiler/brw_fs_generator.cpp | 104 +++++++++++++++-- src/intel/compiler/brw_fs_lower_d2x.cpp | 78 ------------- .../compiler/brw_fs_lower_narrow_conversions.cpp | 123 +++++++++++++++++++++ src/intel/compiler/brw_ir_vec4.h | 37 ++++++- src/intel/compiler/brw_vec4.cpp | 19 +++- src/intel/compiler/brw_vec4.h | 3 +- .../compiler/brw_vec4_dead_code_eliminate.cpp | 2 +- src/intel/compiler/brw_vec4_generator.cpp | 59 ++++++---- src/intel/compiler/brw_vec4_live_variables.h | 4 +- src/intel/compiler/brw_vec4_nir.cpp | 16 +-- src/mesa/drivers/dri/i965/intel_extensions.c | 4 +- src/mesa/drivers/dri/i965/intel_screen.c | 6 +- 19 files changed, 474 insertions(+), 159 deletions(-) delete mode 100644 src/intel/compiler/brw_fs_lower_d2x.cpp create mode 100644 src/intel/compiler/brw_fs_lower_narrow_conversions.cpp -- 2.11.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
