On Tue, 22 Nov 2011 13:44:59 -0800, Chad Versace <chad.vers...@linux.intel.com> wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 11/22/2011 01:04 PM, Eric Anholt wrote: > > --- > > > > There are regressions that look hiz-related on gm45 as well. On 915, > > while this gets things building, it'still in bad shape. Glean > > pixelformats, for example, segfaults at: > > > > 759 colorRegion = irb ? irb->mt->region : NULL;
> All these build fixes look correct to me. > Reviewed-by: Chad Versace <chad.vers...@linux.intel.com> > > As for the assertion failures, replacing conditions like > ir && irb->mt->region > with > irb && irb->mt && irb->mt->region > might be sufficient to reinstate correct behaviour. It was > sufficient for i965. > > If you don't get around to fixing the i915 regressions today, > I can work on them when I'm at my home office tomorrow. The thing that was bothering me was why we had an intel_renderbuffer without storage associated. The trick is that these hardware state update functions are being called outside of the drawing path, since state updates aren't delayed like they are on i965. So you get in here without the dri2 buffer update stuff in intel_context.c being called, and thus the ->mt (previously ->region) is out of date and possibly NULL. The function does gets re-called when we go to actually render and update them. I have to head out of the house, but I'll try and get this patch touched up to not segfault and push it out asap.
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