---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 56 ++++++++++++++++----------------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index fc85f0e..72a0a74 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -644,8 +644,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
switch (instr->op) {
case nir_op_i2f:
case nir_op_u2f:
- case nir_op_i642d:
- case nir_op_u642d:
if (optimize_extract_to_float(instr, result))
return;
inst = bld.MOV(result, op[0]);
@@ -679,13 +677,14 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
break;
}
/* fallthrough */
+ case nir_op_i642d:
+ case nir_op_u642d:
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_i2i64:
case nir_op_i2u64:
case nir_op_u2i64:
case nir_op_u2u64:
- case nir_op_b2i64:
case nir_op_d2f:
case nir_op_d2i:
case nir_op_d2u:
@@ -1086,40 +1085,41 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
inst->saturate = instr->dest.saturate;
break;
+ case nir_op_b2i64:
case nir_op_b2i:
case nir_op_b2f:
bld.MOV(result, negate(op[0]));
break;
case nir_op_f2b:
- bld.CMP(result, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
- break;
-
- case nir_op_i642b:
- case nir_op_d2b: {
- /* two-argument instructions can't take 64-bit immediates */
- fs_reg zero;
- fs_reg tmp;
+ case nir_op_i2b:
+ if (nir_src_bit_size(instr->src[0].src) == 64) {
+ /* two-argument instructions can't take 64-bit immediates */
+ fs_reg zero;
+ fs_reg tmp;
+
+ if (instr->op == nir_op_d2b) {
+ zero = vgrf(glsl_type::double_type);
+ tmp = vgrf(glsl_type::double_type);
+ } else {
+ zero = vgrf(glsl_type::int64_t_type);
+ tmp = vgrf(glsl_type::int64_t_type);
+ }
- if (instr->op == nir_op_d2b) {
- zero = vgrf(glsl_type::double_type);
- tmp = vgrf(glsl_type::double_type);
+ bld.MOV(zero, setup_imm_df(bld, 0.0));
+ /* A SIMD16 execution needs to be split in two instructions, so use
+ * a vgrf instead of the flag register as dst so instruction splitting
+ * works
+ */
+ bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ);
+ bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0));
} else {
- zero = vgrf(glsl_type::int64_t_type);
- tmp = vgrf(glsl_type::int64_t_type);
+ if (instr->op == nir_op_f2b) {
+ bld.CMP(result, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
+ } else {
+ bld.CMP(result, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
+ }
}
-
- bld.MOV(zero, setup_imm_df(bld, 0.0));
- /* A SIMD16 execution needs to be split in two instructions, so use
- * a vgrf instead of the flag register as dst so instruction splitting
- * works
- */
- bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ);
- bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0));
- break;
- }
- case nir_op_i2b:
- bld.CMP(result, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ);
break;
case nir_op_ftrunc:
--
2.5.0.400.gff86faf
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