On 7 March 2017 at 10:44, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote:
> Still not sure we can support miptrees when sampling from
> HTILE enabled textures.
>
> Added the tcCompatible winsys stuff while I'm at it.
Do we trust addrlib here? if so go for it.
Reviewed-by: Dave Airlie <airl...@redhat.com>
>
> Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
> ---
> src/amd/vulkan/radv_radeon_winsys.h | 5 +++++
> src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 26
> ++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_radeon_winsys.h
> b/src/amd/vulkan/radv_radeon_winsys.h
> index 8cf29a38d94..a8a1d2e369f 100644
> --- a/src/amd/vulkan/radv_radeon_winsys.h
> +++ b/src/amd/vulkan/radv_radeon_winsys.h
> @@ -148,6 +148,7 @@ struct radeon_info {
> #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
> #define RADEON_SURF_FMASK (1 << 21)
> #define RADEON_SURF_DISABLE_DCC (1 << 22)
> +#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
>
> #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ##
> _SHIFT) & RADEON_SURF_ ## field ## _MASK)
> #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK)
> << RADEON_SURF_ ## field ## _SHIFT)
> @@ -217,6 +218,10 @@ struct radeon_surf {
>
> uint64_t dcc_size;
> uint64_t dcc_alignment;
> +
> + uint64_t htile_size;
> + uint64_t htile_slice_size;
> + uint64_t htile_alignment;
> };
>
> enum radeon_bo_layout {
> diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> index dc596ff0574..89e84d60a3a 100644
> --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> @@ -260,6 +260,30 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
> }
> }
>
> + if (!is_stencil && AddrSurfInfoIn->flags.depth &&
> + surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
> + ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
> + ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
> + AddrHtileIn.flags.tcCompatible =
> AddrSurfInfoIn->flags.tcCompatible;
> + AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
> + AddrHtileIn.height = AddrSurfInfoOut->height;
> + AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
> + AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
> + AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
> + AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
> + AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
> + AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
> +
> + ret = AddrComputeHtileInfo(addrlib,
> + &AddrHtileIn,
> + &AddrHtileOut);
> +
> + if (ret == ADDR_OK) {
> + surf->htile_size = AddrHtileOut.htileBytes;
> + surf->htile_slice_size = AddrHtileOut.sliceSize;
> + surf->htile_alignment = AddrHtileOut.baseAlign;
> + }
> + }
> return 0;
> }
>
> @@ -455,6 +479,8 @@ static int radv_amdgpu_winsys_surface_init(struct
> radeon_winsys *_ws,
> surf->bo_size = 0;
> surf->dcc_size = 0;
> surf->dcc_alignment = 1;
> + surf->htile_size = surf->htile_slice_size = 0;
> + surf->htile_alignment = 1;
>
> /* Calculate texture layout information. */
> for (level = 0; level <= surf->last_level; level++) {
> --
> 2.11.1
>
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