On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky <b...@bwidawsk.net> wrote:
> v2: Put the commit message as a comment (Topi)
>
> Cc: Topi Pohjolainen <topi.pohjolai...@gmail.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Jason Ekstrand <ja...@jlekstrand.net>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> Acked-by: Daniel Stone <dani...@collabora.com>
> ---
> src/mesa/drivers/dri/i965/intel_screen.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> b/src/mesa/drivers/dri/i965/intel_screen.c
> index 85070bb54d..12b3b071e4 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -1023,7 +1023,10 @@ intel_from_planar(__DRIimage *parent, int plane,
> void *loaderPrivate)
> if (parent == NULL || parent->planar_format == NULL) {
> if (is_aux) {
> offset = parent->aux_offset;
> - stride = ALIGN(parent->pitch / 32, 128);
> + /* Make CCS stride match kernel's expectations. Mesa's internals
> + * expect: stride = ALIGN(parent->pitch / 32, 128)
> + */
> + stride = ALIGN(parent->pitch / 64, 128);
>
Does the kernel expect the alignment to be 128 or 64? Given that ville
likes 64-wide tiles, I think it should be 64. Really, I think the more
accurate calculation would be
stride = ALIGN(parent->pitch, 4096) / 64;
4096 is the stride in bytes in the primary surface required to cross a
single CCS tile. The calculation you have above will work in the sense
that the worst that happens is for it to align up a bit too far. In any
case, what matters is that we a) have enough space and b) exactly match the
kernel's calculation.
--Jason
> height = ALIGN(DIV_ROUND_UP(parent->height, 16), 32);
> dri_format = parent->dri_format;
> goto done;
> --
> 2.11.0
>
>
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