I think of the first patch as a fix to the driver, and the second
patch as a new feature.
On Tue, Jan 24, 2017 at 2:27 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> No piglit regressions on Redwood with these two patches. Matteo's point
> about switching the order of the patches around seems reasonable.
>
> Cheers,
> Nicolai
>
>
> On 24.01.2017 10:20, Nicolai Hähnle wrote:
>>
>> The series looks reasonable to me, so
>>
>> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
>>
>> Please hold off on pushing this for a day or so, to give me or someone
>> else a chance to test this.
>>
>> On 24.01.2017 03:18, Ilia Mirkin wrote:
>>>
>>> Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
>>> ---
>>>
>>> Untested. Can be verified with Xnine. It should pass before 1/2 of
>>> this series,
>>> start failing with it, and pass again with 2/2 in place.
>>>
>>> src/gallium/drivers/r600/r600_pipe.c | 2 +-
>>> src/gallium/drivers/r600/r600_shader.c | 20 +++++++++++++++++---
>>> 2 files changed, 18 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/src/gallium/drivers/r600/r600_pipe.c
>>> b/src/gallium/drivers/r600/r600_pipe.c
>>> index 98ceebf..d126d37 100644
>>> --- a/src/gallium/drivers/r600/r600_pipe.c
>>> +++ b/src/gallium/drivers/r600/r600_pipe.c
>>> @@ -286,6 +286,7 @@ static int r600_get_param(struct pipe_screen*
>>> pscreen, enum pipe_cap param)
>>> case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
>>> case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
>>> case PIPE_CAP_CLEAR_TEXTURE:
>>> + case PIPE_CAP_TGSI_MUL_ZERO_WINS:
>>> return 1;
>>>
>>> case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
>>> @@ -378,7 +379,6 @@ static int r600_get_param(struct pipe_screen*
>>> pscreen, enum pipe_cap param)
>>> case PIPE_CAP_NATIVE_FENCE_FD:
>>> case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
>>> case PIPE_CAP_TGSI_FS_FBFETCH:
>>> - case PIPE_CAP_TGSI_MUL_ZERO_WINS:
>>> return 0;
>>>
>>> case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
>>> diff --git a/src/gallium/drivers/r600/r600_shader.c
>>> b/src/gallium/drivers/r600/r600_shader.c
>>> index 0114f8f..b692e7f 100644
>>> --- a/src/gallium/drivers/r600/r600_shader.c
>>> +++ b/src/gallium/drivers/r600/r600_shader.c
>>> @@ -3906,6 +3906,11 @@ static int tgsi_op2_s(struct r600_shader_ctx
>>> *ctx, int swap, int trans_only)
>>> int i, j, r, lasti = tgsi_last_instruction(write_mask);
>>> /* use temp register if trans_only and more than one dst
>>> component */
>>> int use_tmp = trans_only && (write_mask ^ (1 << lasti));
>>> + unsigned op = ctx->inst_info->op;
>>> +
>>> + if (op == ALU_OP2_MUL_IEEE &&
>>> + ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
>>> + op = ALU_OP2_MUL;
>>>
>>> for (i = 0; i <= lasti; i++) {
>>> if (!(write_mask & (1 << i)))
>>> @@ -3919,7 +3924,7 @@ static int tgsi_op2_s(struct r600_shader_ctx
>>> *ctx, int swap, int trans_only)
>>> } else
>>> tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
>>>
>>> - alu.op = ctx->inst_info->op;
>>> + alu.op = op;
>>> if (!swap) {
>>> for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
>>> r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
>>> @@ -6543,6 +6548,11 @@ static int tgsi_op3(struct r600_shader_ctx *ctx)
>>> int i, j, r;
>>> int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
>>> int temp_regs[4];
>>> + unsigned op = ctx->inst_info->op;
>>> +
>>> + if (op == ALU_OP3_MULADD_IEEE &&
>>> + ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
>>> + op = ALU_OP3_MULADD;
>>>
>>> for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
>>> temp_regs[j] = 0;
>>> @@ -6554,7 +6564,7 @@ static int tgsi_op3(struct r600_shader_ctx *ctx)
>>> continue;
>>>
>>> memset(&alu, 0, sizeof(struct r600_bytecode_alu));
>>> - alu.op = ctx->inst_info->op;
>>> + alu.op = op;
>>> for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
>>> r = tgsi_make_src_for_op3(ctx, temp_regs[j], i,
>>> &alu.src[j], &ctx->src[j]);
>>> if (r)
>>> @@ -6580,10 +6590,14 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
>>> struct tgsi_full_instruction *inst =
>>> &ctx->parse.FullToken.FullInstruction;
>>> struct r600_bytecode_alu alu;
>>> int i, j, r;
>>> + unsigned op = ctx->inst_info->op;
>>> + if (op == ALU_OP2_DOT4_IEEE &&
>>> + ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
>>> + op = ALU_OP2_DOT4;
>>>
>>> for (i = 0; i < 4; i++) {
>>> memset(&alu, 0, sizeof(struct r600_bytecode_alu));
>>> - alu.op = ctx->inst_info->op;
>>> + alu.op = op;
>>> for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
>>> r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
>>> }
>>>
>
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