From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_descriptors.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index fa3eaad..837f393 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -930,48 +930,49 @@ static void si_vertex_buffers_begin_new_cs(struct
si_context *sctx)
if (!desc->buffer)
return;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
}
bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
{
+ struct si_vertex_element *velems = sctx->vertex_elements;
struct si_descriptors *desc = &sctx->vertex_buffers;
bool bound[SI_NUM_VERTEX_BUFFERS] = {};
- unsigned i, count = sctx->vertex_elements->count;
+ unsigned i, count = velems->count;
uint64_t va;
uint32_t *ptr;
- if (!sctx->vertex_buffers_dirty)
- return true;
- if (!count || !sctx->vertex_elements)
+ if (!sctx->vertex_buffers_dirty || !count || !velems)
return true;
+ unsigned fix_size3 = velems->fix_size3;
+
/* Vertex buffer descriptors are the only ones which are uploaded
* directly through a staging buffer and don't go through
* the fine-grained upload path.
*/
u_upload_alloc(sctx->b.uploader, 0, count * 16, 256,
&desc->buffer_offset,
(struct pipe_resource**)&desc->buffer, (void**)&ptr);
if (!desc->buffer)
return false;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
assert(count <= SI_NUM_VERTEX_BUFFERS);
for (i = 0; i < count; i++) {
- struct pipe_vertex_element *ve =
&sctx->vertex_elements->elements[i];
+ struct pipe_vertex_element *ve = &velems->elements[i];
struct pipe_vertex_buffer *vb;
struct r600_resource *rbuffer;
unsigned offset;
uint32_t *desc = &ptr[i*4];
vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
rbuffer = (struct r600_resource*)vb->buffer;
if (!rbuffer) {
memset(desc, 0, 16);
continue;
@@ -981,48 +982,48 @@ bool si_upload_vertex_buffer_descriptors(struct
si_context *sctx)
va = rbuffer->gpu_address + offset;
/* Fill in T# buffer resource description */
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride);
if (sctx->b.chip_class <= CIK && vb->stride) {
/* Round up by rounding down and adding 1 */
desc[2] = (vb->buffer->width0 - offset -
- sctx->vertex_elements->format_size[i]) /
+ velems->format_size[i]) /
vb->stride + 1;
} else {
uint32_t size3;
desc[2] = vb->buffer->width0 - offset;
/* For attributes of size 3 with byte or short
* components, we use a 4-component data format.
*
* As a consequence, we have to round the buffer size
* up so that the hardware sees four components as
* being inside the buffer if and only if the first
* three components are in the buffer.
*
* Since the offset and stride are guaranteed to be
* 4-byte aligned, this alignment will never cross the
* winsys buffer boundary.
*/
- size3 = (sctx->vertex_elements->fix_size3 >> (2 * i)) &
3;
+ size3 = (fix_size3 >> (2 * i)) & 3;
if (vb->stride && size3) {
assert(offset % 4 == 0 && vb->stride % 4 == 0);
assert(size3 <= 2);
desc[2] = align(desc[2], size3 * 2);
}
}
- desc[3] = sctx->vertex_elements->rsrc_word3[i];
+ desc[3] = velems->rsrc_word3[i];
if (!bound[ve->vertex_buffer_index]) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)vb->buffer,
RADEON_USAGE_READ,
RADEON_PRIO_VERTEX_BUFFER);
bound[ve->vertex_buffer_index] = true;
}
}
/* Don't flush the const cache. It would have a very negative effect
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
