Blorp blits and clears use heavy hammer before and after each operation. This is pipe control with almost all the bits set simultaneously:
PIPE_CONTROL_RENDER_TARGET_FLUSH PIPE_CONTROL_INSTRUCTION_INVALIDATE PIPE_CONTROL_CONST_CACHE_INVALIDATE PIPE_CONTROL_DEPTH_CACHE_FLUSH PIPE_CONTROL_VF_CACHE_INVALIDATE PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE PIPE_CONTROL_CS_STALL Normal drawing in turn only flushes before render, and even then conditionally by consulting render cache against destination and source (calls brw_render_cache_set_check_flush()). Afterwards instead of flushing again, render cache is updated to signal that flushing is needed whenever the just targeted surface is involved. This series changes blorp blits and clears to use the same mechanism. It also adds explicit flushes and stalls mandated by the spec for depth/hiz/fast clear operations. It looks that the current unconditional flushing is hiding the need for these. CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Mark Janes <mark.a.ja...@intel.com> Topi Pohjolainen (4): i965/blorp: Do pre-draw flush with two pipe-control writes i965: Make depth clear flushing more explicit i965/gen6: Issue direct depth stall and flush after depth clear i965/blorp: Make post draw flush more explicit src/mesa/drivers/dri/i965/brw_blorp.c | 22 ++++++++++++++ src/mesa/drivers/dri/i965/brw_clear.c | 45 ++++++++++++++++++++++------ src/mesa/drivers/dri/i965/gen8_depth_state.c | 16 ++++++++++ src/mesa/drivers/dri/i965/genX_blorp_exec.c | 10 +++---- 4 files changed, 79 insertions(+), 14 deletions(-) -- 2.5.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
