Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
On Mon, Jan 16, 2017 at 4:07 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
>
> On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote:
> > Only caller, brw_workaround_depthstencil_alignment(), returns
> > early for gen6+.
> >
> > While at it, reduce scope for brw_get_depthstencil_tile_masks() as
> > well.
> >
> > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> > ---
> > src/mesa/drivers/dri/i965/brw_context.h | 6 ------
> > src/mesa/drivers/dri/i965/brw_misc_state.c | 18 ++----------------
> > 2 files changed, 2 insertions(+), 22 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> > b/src/mesa/drivers/dri/i965/brw_context.h
> > index ff3f861..4176853 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.h
> > +++ b/src/mesa/drivers/dri/i965/brw_context.h
> > @@ -1279,12 +1279,6 @@ brw_meta_resolve_color(struct brw_context
> > *brw,
> > /*==================================================================
> > ====
> > * brw_misc_state.c
> > */
> > -void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
> > *depth_mt,
> > - uint32_t depth_level,
> > - uint32_t depth_layer,
> > - struct intel_mipmap_tree
> > *stencil_mt,
> > - uint32_t *out_tile_mask_x,
> > - uint32_t *out_tile_mask_y);
> > void brw_workaround_depthstencil_alignment(struct brw_context *brw,
> > GLbitfield clear_mask);
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> > b/src/mesa/drivers/dri/i965/brw_misc_state.c
> > index 40a8d07..616c0df 100644
> > --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> > @@ -165,7 +165,7 @@ brw_depthbuffer_format(struct brw_context *brw)
> > * packet. If the 3 buffers don't agree on the drawing offset ANDed
> > with this
> > * mask, then we're in trouble.
> > */
> > -void
> > +static void
> > brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
> > uint32_t depth_level,
> > uint32_t depth_layer,
> > @@ -179,21 +179,7 @@ brw_get_depthstencil_tile_masks(struct
> > intel_mipmap_tree *depth_mt,
> > intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
> > depth_mt->cpp,
> > &tile_mask_x, &tile_mask_y);
> > -
> > - if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
> > - uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
> > - intel_get_tile_masks(depth_mt->hiz_buf->mt->tiling,
> > - depth_mt->hiz_buf->mt->tr_mode,
> > - depth_mt->hiz_buf->mt->cpp,
> > - &hiz_tile_mask_x,
> > - &hiz_tile_mask_y);
> > -
> > - /* Each HiZ row represents 2 rows of pixels */
> > - hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;
> > -
> > - tile_mask_x |= hiz_tile_mask_x;
> > - tile_mask_y |= hiz_tile_mask_y;
> > - }
> > + assert(!intel_miptree_level_has_hiz(depth_mt, depth_level));
> > }
> >
> > if (stencil_mt) {
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