From: Marek Olšák <marek.ol...@amd.com>
It's redundant with the source modifier.
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 2 +-
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 16 +---------
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 2 +-
src/gallium/auxiliary/nir/tgsi_to_nir.c | 1 -
src/gallium/auxiliary/tgsi/tgsi_exec.c | 4 ---
src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +-
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h | 1 -
src/gallium/auxiliary/tgsi/tgsi_util.c | 1 -
src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 5 ----
src/gallium/drivers/i915/i915_fpc_optimize.c | 1 -
src/gallium/drivers/i915/i915_fpc_translate.c | 9 ------
src/gallium/drivers/ilo/shader/toy_tgsi.c | 4 ---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 --
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 3 --
src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c | 3 --
src/gallium/drivers/r300/r300_tgsi_to_rc.c | 1 -
src/gallium/drivers/r600/r600_shader.c | 9 ++----
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 2 --
src/gallium/drivers/svga/svga_tgsi_insn.c | 1 -
src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 24 ---------------
src/gallium/include/pipe/p_shader_tokens.h | 2 +-
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 35 ++++++++++++++++++----
src/mesa/state_tracker/st_mesa_to_tgsi.c | 6 ++--
23 files changed, 41 insertions(+), 96 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index 68ac695..d368f38 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -353,21 +353,21 @@ lp_build_emit_fetch(
assert(0 && "invalid src register in emit_fetch()");
return bld_base->base.undef;
}
if (reg->Register.Absolute) {
switch (stype) {
case TGSI_TYPE_FLOAT:
case TGSI_TYPE_DOUBLE:
case TGSI_TYPE_UNTYPED:
/* modifiers on movs assume data is float */
- res = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_ABS, res);
+ res = lp_build_abs(&bld_base->base, res);
break;
case TGSI_TYPE_UNSIGNED:
case TGSI_TYPE_SIGNED:
case TGSI_TYPE_UNSIGNED64:
case TGSI_TYPE_SIGNED64:
case TGSI_TYPE_VOID:
default:
/* abs modifier is only legal on floating point types */
assert(0);
break;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index 9c6fc4b..7d939e8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -492,22 +492,21 @@ static struct lp_build_tgsi_action lit_action = {
static void
log_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMValueRef abs_x, log_abs_x, flr_log_abs_x, ex2_flr_log_abs_x;
/* abs( src0.x) */
- abs_x = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_ABS,
- emit_data->args[0] /* src0.x */);
+ abs_x = lp_build_abs(&bld_base->base, emit_data->args[0] /* src0.x */);
/* log( abs( src0.x ) ) */
log_abs_x = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_LG2,
abs_x);
/* floor( log( abs( src0.x ) ) ) */
flr_log_abs_x = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR,
log_abs_x);
/* dst.x */
emit_data->output[TGSI_CHAN_X] = flr_log_abs_x;
@@ -1405,32 +1404,20 @@ lp_set_default_actions(struct lp_build_tgsi_context *
bld_base)
bld_base->op_actions[TGSI_OPCODE_U642D].emit = u642d_emit;
}
/* CPU Only default actions */
/* These actions are CPU only, because they could potentially output SSE
* intrinsics.
*/
-/* TGSI_OPCODE_ABS (CPU Only)*/
-
-static void
-abs_emit_cpu(
- const struct lp_build_tgsi_action * action,
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- emit_data->output[emit_data->chan] = lp_build_abs(&bld_base->base,
- emit_data->args[0]);
-}
-
/* TGSI_OPCODE_ADD (CPU Only) */
static void
add_emit_cpu(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
emit_data->output[emit_data->chan] = lp_build_add(&bld_base->base,
emit_data->args[0], emit_data->args[1]);
}
@@ -2581,21 +2568,20 @@ u64shr_emit_cpu(
LLVMValueRef masked_count = lp_build_and(uint_bld, emit_data->args[1],
mask);
emit_data->output[emit_data->chan] = lp_build_shr(uint_bld,
emit_data->args[0],
masked_count);
}
void
lp_set_default_actions_cpu(
struct lp_build_tgsi_context * bld_base)
{
lp_set_default_actions(bld_base);
- bld_base->op_actions[TGSI_OPCODE_ABS].emit = abs_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_AND].emit = and_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = ceil_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_COS].emit = cos_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_CMP].emit = cmp_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_DIV].emit = div_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_EX2].emit = ex2_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_F2I].emit = f2i_emit_cpu;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
index 610283d..a5e439f 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
@@ -514,21 +514,21 @@ lp_emit_instruction_aos(
case TGSI_OPCODE_RCP:
/* TGSI_OPCODE_RECIP */
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
dst0 = lp_build_rcp(&bld->bld_base.base, src0);
break;
case TGSI_OPCODE_RSQ:
/* TGSI_OPCODE_RECIPSQRT */
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
- tmp0 = lp_build_emit_llvm_unary(&bld->bld_base, TGSI_OPCODE_ABS, src0);
+ tmp0 = lp_build_abs(&bld->bld_base.base, src0);
dst0 = lp_build_rsqrt(&bld->bld_base.base, tmp0);
break;
case TGSI_OPCODE_EXP:
return FALSE;
case TGSI_OPCODE_LOG:
return FALSE;
case TGSI_OPCODE_MUL:
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index c7afe96..af4a6e0 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1540,21 +1540,20 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_SQRT] = nir_op_fsqrt,
[TGSI_OPCODE_DP2A] = 0,
[TGSI_OPCODE_FRC] = nir_op_ffract,
[TGSI_OPCODE_CLAMP] = 0,
[TGSI_OPCODE_FLR] = nir_op_ffloor,
[TGSI_OPCODE_ROUND] = nir_op_fround_even,
[TGSI_OPCODE_EX2] = nir_op_fexp2,
[TGSI_OPCODE_LG2] = nir_op_flog2,
[TGSI_OPCODE_POW] = nir_op_fpow,
[TGSI_OPCODE_XPD] = 0,
- [TGSI_OPCODE_ABS] = nir_op_fabs,
[TGSI_OPCODE_DPH] = 0,
[TGSI_OPCODE_COS] = nir_op_fcos,
[TGSI_OPCODE_DDX] = nir_op_fddx,
[TGSI_OPCODE_DDY] = nir_op_fddy,
[TGSI_OPCODE_KILL] = 0,
[TGSI_OPCODE_PK2H] = 0, /* XXX */
[TGSI_OPCODE_PK2US] = 0, /* XXX */
[TGSI_OPCODE_PK4B] = 0, /* XXX */
[TGSI_OPCODE_PK4UB] = 0, /* XXX */
[TGSI_OPCODE_SEQ] = nir_op_seq,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 7b5c56d..2f89de6 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -5249,24 +5249,20 @@ exec_instruction(
break;
case TGSI_OPCODE_POW:
exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT,
TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_XPD:
exec_xpd(mach, inst);
break;
- case TGSI_OPCODE_ABS:
- exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT,
TGSI_EXEC_DATA_FLOAT);
- break;
-
case TGSI_OPCODE_DPH:
exec_dph(mach, inst);
break;
case TGSI_OPCODE_COS:
exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT,
TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_DDX:
exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT,
TGSI_EXEC_DATA_FLOAT);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 37549aa..9b2431f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -63,21 +63,21 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "EX2", TGSI_OPCODE_EX2 },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "LG2", TGSI_OPCODE_LG2 },
{ 1, 2, 0, 0, 0, 0, 0, REPL, "POW", TGSI_OPCODE_POW },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "U2I64", TGSI_OPCODE_U2I64 },
- { 1, 1, 0, 0, 0, 0, 0, COMP, "ABS", TGSI_OPCODE_ABS },
+ { 1, 1, 0, 0, 0, 0, 0, COMP, "", 33 }, /* removed */
{ 1, 1, 0, 0, 0, 0, 0, COMP, "I2I64", TGSI_OPCODE_I2I64 },
{ 1, 2, 0, 0, 0, 0, 0, REPL, "DPH", TGSI_OPCODE_DPH },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "COS", TGSI_OPCODE_COS },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "DDY", TGSI_OPCODE_DDY },
{ 0, 0, 0, 0, 0, 0, 0, NONE, "KILL", TGSI_OPCODE_KILL },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK2H", TGSI_OPCODE_PK2H },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK2US", TGSI_OPCODE_PK2US },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK4B", TGSI_OPCODE_PK4B },
{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK4UB", TGSI_OPCODE_PK4UB },
diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
index d8752ce..d78dd66 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
@@ -78,21 +78,20 @@ OP13(LRP)
OP11(SQRT)
OP13(DP2A)
OP11(FRC)
OP13(CLAMP)
OP11(FLR)
OP11(ROUND)
OP11(EX2)
OP11(LG2)
OP12(POW)
OP12(XPD)
-OP11(ABS)
OP12(DPH)
OP11(COS)
OP11(DDX)
OP11(DDY)
OP11(DDX_FINE)
OP11(DDY_FINE)
OP00(KILL)
OP11(PK2H)
OP11(PK2US)
OP11(PK4B)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c
b/src/gallium/auxiliary/tgsi/tgsi_util.c
index fbe2962..4f02829 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -194,21 +194,20 @@ tgsi_util_get_inst_usage_mask(const struct
tgsi_full_instruction *inst,
case TGSI_OPCODE_MAD:
case TGSI_OPCODE_SUB:
case TGSI_OPCODE_LRP:
case TGSI_OPCODE_FMA:
case TGSI_OPCODE_FRC:
case TGSI_OPCODE_CEIL:
case TGSI_OPCODE_CLAMP:
case TGSI_OPCODE_FLR:
case TGSI_OPCODE_ROUND:
case TGSI_OPCODE_POW:
- case TGSI_OPCODE_ABS:
case TGSI_OPCODE_COS:
case TGSI_OPCODE_SIN:
case TGSI_OPCODE_DDX:
case TGSI_OPCODE_DDY:
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_SGT:
case TGSI_OPCODE_SLE:
case TGSI_OPCODE_SNE:
case TGSI_OPCODE_SSG:
case TGSI_OPCODE_CMP:
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
index 39418fc..2ffd8cd 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
@@ -1073,25 +1073,20 @@ translate_instruction(struct fd2_compile_context *ctx,
instr = ir2_instr_create_alu(cf, FLOORv, ~0);
add_regs_vector_1(ctx, inst, instr);
break;
case TGSI_OPCODE_EX2:
instr = ir2_instr_create_alu(cf, ~0, EXP_IEEE);
add_regs_scalar_1(ctx, inst, instr);
break;
case TGSI_OPCODE_POW:
translate_pow(ctx, inst);
break;
- case TGSI_OPCODE_ABS:
- instr = ir2_instr_create_alu(cf, MAXv, ~0);
- add_regs_vector_1(ctx, inst, instr);
- instr->regs[1]->flags |= IR2_REG_NEGATE; /* src0 */
- break;
case TGSI_OPCODE_COS:
case TGSI_OPCODE_SIN:
translate_trig(ctx, inst, opc);
break;
case TGSI_OPCODE_TEX:
case TGSI_OPCODE_TXP:
translate_tex(ctx, inst, opc);
break;
case TGSI_OPCODE_CMP:
instr = ir2_instr_create_alu(cf, CNDGTEv, ~0);
diff --git a/src/gallium/drivers/i915/i915_fpc_optimize.c
b/src/gallium/drivers/i915/i915_fpc_optimize.c
index a2b6d27..7c3b9a9 100644
--- a/src/gallium/drivers/i915/i915_fpc_optimize.c
+++ b/src/gallium/drivers/i915/i915_fpc_optimize.c
@@ -69,21 +69,20 @@ static boolean same_src_reg(struct i915_full_src_register
*d1, struct i915_full_
d1->Register.Negate == d2->Register.Negate);
}
static const struct {
boolean is_texture;
boolean commutes;
unsigned neutral_element;
unsigned num_dst;
unsigned num_src;
} op_table [TGSI_OPCODE_LAST] = {
- [ TGSI_OPCODE_ABS ] = { false, false, 0, 1, 1 },
[ TGSI_OPCODE_ADD ] = { false, true, TGSI_SWIZZLE_ZERO, 1, 2 },
[ TGSI_OPCODE_CEIL ] = { false, false, 0, 1, 1 },
[ TGSI_OPCODE_CMP ] = { false, false, 0, 1, 2 },
[ TGSI_OPCODE_COS ] = { false, false, 0, 1, 1 },
[ TGSI_OPCODE_DDX ] = { false, false, 0, 1, 0 },
[ TGSI_OPCODE_DDY ] = { false, false, 0, 1, 0 },
[ TGSI_OPCODE_DP2 ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2 },
[ TGSI_OPCODE_DP3 ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2 },
[ TGSI_OPCODE_DP4 ] = { false, true, TGSI_SWIZZLE_ONE, 1, 2 },
[ TGSI_OPCODE_DPH ] = { false, false, 0, 1, 2 },
diff --git a/src/gallium/drivers/i915/i915_fpc_translate.c
b/src/gallium/drivers/i915/i915_fpc_translate.c
index 72b9092..80caf31 100644
--- a/src/gallium/drivers/i915/i915_fpc_translate.c
+++ b/src/gallium/drivers/i915/i915_fpc_translate.c
@@ -493,29 +493,20 @@ emit_simple_arith_swap2(struct i915_fp_compile *p,
static void
i915_translate_instruction(struct i915_fp_compile *p,
const struct i915_full_instruction *inst,
struct i915_fragment_shader *fs)
{
uint writemask;
uint src0, src1, src2, flags;
uint tmp = 0;
switch (inst->Instruction.Opcode) {
- case TGSI_OPCODE_ABS:
- src0 = src_vector(p, &inst->Src[0], fs);
- i915_emit_arith(p,
- A0_MAX,
- get_result_vector(p, &inst->Dst[0]),
- get_result_flags(inst), 0,
- src0, negate(src0, 1, 1, 1, 1), 0);
- break;
-
case TGSI_OPCODE_ADD:
emit_simple_arith(p, inst, A0_ADD, 2, fs);
break;
case TGSI_OPCODE_CEIL:
src0 = src_vector(p, &inst->Src[0], fs);
tmp = i915_get_utemp(p);
flags = get_result_flags(inst);
i915_emit_arith(p,
A0_FLR,
diff --git a/src/gallium/drivers/ilo/shader/toy_tgsi.c
b/src/gallium/drivers/ilo/shader/toy_tgsi.c
index e5fbb6e..a88f189 100644
--- a/src/gallium/drivers/ilo/shader/toy_tgsi.c
+++ b/src/gallium/drivers/ilo/shader/toy_tgsi.c
@@ -51,21 +51,20 @@ static const struct {
/* a later pass will move src[2] to accumulator */
[TGSI_OPCODE_MAD] = { GEN6_OPCODE_MAC, 1, 3 },
[TGSI_OPCODE_SUB] = { GEN6_OPCODE_ADD, 1, 2 },
[TGSI_OPCODE_SQRT] = { TOY_OPCODE_SQRT, 1, 1 },
[TGSI_OPCODE_FRC] = { GEN6_OPCODE_FRC, 1, 1 },
[TGSI_OPCODE_FLR] = { GEN6_OPCODE_RNDD, 1, 1 },
[TGSI_OPCODE_ROUND] = { GEN6_OPCODE_RNDE, 1, 1 },
[TGSI_OPCODE_EX2] = { TOY_OPCODE_EXP, 1, 1 },
[TGSI_OPCODE_LG2] = { TOY_OPCODE_LOG, 1, 1 },
[TGSI_OPCODE_POW] = { TOY_OPCODE_POW, 1, 2 },
- [TGSI_OPCODE_ABS] = { GEN6_OPCODE_MOV, 1, 1 },
[TGSI_OPCODE_DPH] = { GEN6_OPCODE_DPH, 1, 2 },
[TGSI_OPCODE_COS] = { TOY_OPCODE_COS, 1, 1 },
[TGSI_OPCODE_KILL] = { TOY_OPCODE_KIL, 0, 0 },
[TGSI_OPCODE_SIN] = { TOY_OPCODE_SIN, 1, 1 },
[TGSI_OPCODE_ARR] = { GEN6_OPCODE_RNDZ, 1, 1 },
[TGSI_OPCODE_DP2] = { GEN6_OPCODE_DP2, 1, 2 },
[TGSI_OPCODE_IF] = { GEN6_OPCODE_IF, 0, 1 },
[TGSI_OPCODE_UIF] = { GEN6_OPCODE_IF, 0, 1 },
[TGSI_OPCODE_ELSE] = { GEN6_OPCODE_ELSE, 0, 0 },
[TGSI_OPCODE_ENDIF] = { GEN6_OPCODE_ENDIF, 0, 0 },
@@ -141,21 +140,20 @@ aos_simple(struct toy_compiler *tc,
cond_modifier = GEN6_COND_L;
break;
case TGSI_OPCODE_MAX:
case TGSI_OPCODE_IMAX:
case TGSI_OPCODE_UMAX:
cond_modifier = GEN6_COND_GE;
break;
case TGSI_OPCODE_SUB:
src[1] = tsrc_negate(src[1]);
break;
- case TGSI_OPCODE_ABS:
case TGSI_OPCODE_IABS:
src[0] = tsrc_absolute(src[0]);
break;
case TGSI_OPCODE_IF:
cond_modifier = GEN6_COND_NZ;
num_src = 2;
assert(src[0].type == TOY_TYPE_F);
src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
src[1] = tsrc_imm_f(0.0f);
break;
@@ -783,21 +781,20 @@ static const toy_tgsi_translate
aos_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_SQRT] = aos_simple,
[TGSI_OPCODE_DP2A] = aos_DP2A,
[TGSI_OPCODE_FRC] = aos_simple,
[TGSI_OPCODE_CLAMP] = aos_CLAMP,
[TGSI_OPCODE_FLR] = aos_simple,
[TGSI_OPCODE_ROUND] = aos_simple,
[TGSI_OPCODE_EX2] = aos_simple,
[TGSI_OPCODE_LG2] = aos_simple,
[TGSI_OPCODE_POW] = aos_simple,
[TGSI_OPCODE_XPD] = aos_XPD,
- [TGSI_OPCODE_ABS] = aos_simple,
[TGSI_OPCODE_DPH] = aos_simple,
[TGSI_OPCODE_COS] = aos_simple,
[TGSI_OPCODE_DDX] = aos_unsupported,
[TGSI_OPCODE_DDY] = aos_unsupported,
[TGSI_OPCODE_KILL] = aos_simple,
[TGSI_OPCODE_PK2H] = aos_PK2H,
[TGSI_OPCODE_PK2US] = aos_unsupported,
[TGSI_OPCODE_PK4B] = aos_unsupported,
[TGSI_OPCODE_PK4UB] = aos_unsupported,
[TGSI_OPCODE_SEQ] = aos_set_on_cond,
@@ -1326,21 +1323,20 @@ static const toy_tgsi_translate
soa_translate_table[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_SQRT] = soa_scalar_replicate,
[TGSI_OPCODE_DP2A] = soa_dot_product,
[TGSI_OPCODE_FRC] = soa_per_channel,
[TGSI_OPCODE_CLAMP] = soa_per_channel,
[TGSI_OPCODE_FLR] = soa_per_channel,
[TGSI_OPCODE_ROUND] = soa_per_channel,
[TGSI_OPCODE_EX2] = soa_scalar_replicate,
[TGSI_OPCODE_LG2] = soa_scalar_replicate,
[TGSI_OPCODE_POW] = soa_scalar_replicate,
[TGSI_OPCODE_XPD] = soa_XPD,
- [TGSI_OPCODE_ABS] = soa_per_channel,
[TGSI_OPCODE_DPH] = soa_dot_product,
[TGSI_OPCODE_COS] = soa_scalar_replicate,
[TGSI_OPCODE_DDX] = soa_partial_derivative,
[TGSI_OPCODE_DDY] = soa_partial_derivative,
[TGSI_OPCODE_KILL] = soa_passthrough,
[TGSI_OPCODE_PK2H] = soa_PK2H,
[TGSI_OPCODE_PK2US] = soa_unsupported,
[TGSI_OPCODE_PK4B] = soa_unsupported,
[TGSI_OPCODE_PK4UB] = soa_unsupported,
[TGSI_OPCODE_SEQ] = soa_per_channel,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 91cef81..b919098 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -724,22 +724,20 @@ static nv50_ir::operation translateOpcode(uint opcode)
NV50_IR_OPCODE_CASE(MAD, MAD);
NV50_IR_OPCODE_CASE(FMA, FMA);
NV50_IR_OPCODE_CASE(SUB, SUB);
NV50_IR_OPCODE_CASE(FLR, FLOOR);
NV50_IR_OPCODE_CASE(ROUND, CVT);
NV50_IR_OPCODE_CASE(EX2, EX2);
NV50_IR_OPCODE_CASE(LG2, LG2);
NV50_IR_OPCODE_CASE(POW, POW);
- NV50_IR_OPCODE_CASE(ABS, ABS);
-
NV50_IR_OPCODE_CASE(COS, COS);
NV50_IR_OPCODE_CASE(DDX, DFDX);
NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
NV50_IR_OPCODE_CASE(DDY, DFDY);
NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
NV50_IR_OPCODE_CASE(KILL, DISCARD);
NV50_IR_OPCODE_CASE(SEQ, SET);
NV50_IR_OPCODE_CASE(SGT, SET);
NV50_IR_OPCODE_CASE(SIN, SIN);
@@ -3004,21 +3002,20 @@ Converter::handleInstruction(const struct
tgsi_full_instruction *insn)
case TGSI_OPCODE_SAD:
case TGSI_OPCODE_FMA:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
src0 = fetchSrc(0, c);
src1 = fetchSrc(1, c);
src2 = fetchSrc(2, c);
mkOp3(op, dstTy, dst0[c], src0, src1, src2);
}
break;
case TGSI_OPCODE_MOV:
- case TGSI_OPCODE_ABS:
case TGSI_OPCODE_CEIL:
case TGSI_OPCODE_FLR:
case TGSI_OPCODE_TRUNC:
case TGSI_OPCODE_RCP:
case TGSI_OPCODE_SQRT:
case TGSI_OPCODE_IABS:
case TGSI_OPCODE_INEG:
case TGSI_OPCODE_NOT:
case TGSI_OPCODE_DDX:
case TGSI_OPCODE_DDY:
diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
index dab42e1..d031c68 100644
--- a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
@@ -526,23 +526,20 @@ nvfx_fragprog_parse_instruction(struct nvfx_fpc *fpc,
NOUVEAU_ERR("bad src file\n");
return false;
}
}
dst = tgsi_dst(fpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
sat = finst->Instruction.Saturate;
switch (finst->Instruction.Opcode) {
- case TGSI_OPCODE_ABS:
- nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
- break;
case TGSI_OPCODE_ADD:
nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
break;
case TGSI_OPCODE_CEIL:
tmp = nvfx_src(temp(fpc));
nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, neg(src[0]), none, none));
nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, neg(tmp), none, none));
break;
case TGSI_OPCODE_CMP:
insn = arith(0, MOV, none.reg, mask, src[0], none, none);
diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
b/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
index b39c4b7..a802c43 100644
--- a/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
@@ -542,23 +542,20 @@ nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc,
if(finst->Instruction.Saturate) {
assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL);
if (vpc->is_nv4x)
sat = true;
else
if(dst.type != NVFXSR_TEMP)
dst = temp(vpc);
}
switch (finst->Instruction.Opcode) {
- case TGSI_OPCODE_ABS:
- nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none,
none));
- break;
case TGSI_OPCODE_ADD:
nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1]));
break;
case TGSI_OPCODE_ARL:
nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none));
break;
case TGSI_OPCODE_CEIL:
tmp = nvfx_src(temp(vpc));
nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, neg(src[0]), none,
none));
nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none));
diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
index 23ed2cf..9d1e59f 100644
--- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
+++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
@@ -54,21 +54,20 @@ static unsigned translate_opcode(unsigned opcode)
case TGSI_OPCODE_LRP: return RC_OPCODE_LRP;
/* case TGSI_OPCODE_DP2A: return RC_OPCODE_DP2A; */
case TGSI_OPCODE_FRC: return RC_OPCODE_FRC;
case TGSI_OPCODE_CLAMP: return RC_OPCODE_CLAMP;
case TGSI_OPCODE_FLR: return RC_OPCODE_FLR;
case TGSI_OPCODE_ROUND: return RC_OPCODE_ROUND;
case TGSI_OPCODE_EX2: return RC_OPCODE_EX2;
case TGSI_OPCODE_LG2: return RC_OPCODE_LG2;
case TGSI_OPCODE_POW: return RC_OPCODE_POW;
case TGSI_OPCODE_XPD: return RC_OPCODE_XPD;
- case TGSI_OPCODE_ABS: return RC_OPCODE_ABS;
case TGSI_OPCODE_DPH: return RC_OPCODE_DPH;
case TGSI_OPCODE_COS: return RC_OPCODE_COS;
case TGSI_OPCODE_DDX: return RC_OPCODE_DDX;
case TGSI_OPCODE_DDY: return RC_OPCODE_DDY;
case TGSI_OPCODE_KILL: return RC_OPCODE_KILP;
/* case TGSI_OPCODE_PK2H: return RC_OPCODE_PK2H; */
/* case TGSI_OPCODE_PK2US: return RC_OPCODE_PK2US; */
/* case TGSI_OPCODE_PK4B: return RC_OPCODE_PK4B; */
/* case TGSI_OPCODE_PK4UB: return RC_OPCODE_PK4UB; */
case TGSI_OPCODE_SEQ: return RC_OPCODE_SEQ;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index b5e7b7d..c2996aa 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3929,23 +3929,20 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int
swap, int trans_only)
}
} else {
r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
}
/* handle some special cases */
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_SUB:
r600_bytecode_src_toggle_neg(&alu.src[1]);
break;
- case TGSI_OPCODE_ABS:
- r600_bytecode_src_set_abs(&alu.src[0]);
- break;
default:
break;
}
if (i == lasti || trans_only) {
alu.last = 1;
}
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
return r;
}
@@ -9018,21 +9015,21 @@ static const struct r600_shader_tgsi_instruction
r600_shader_tgsi_instruction[]
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
[TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE,
tgsi_trans_srcx_replicate},
[TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE,
tgsi_trans_srcx_replicate},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
+ [33] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
[TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
[TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
[TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /*
unconditional kill */
[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
@@ -9217,21 +9214,21 @@ static const struct r600_shader_tgsi_instruction
eg_shader_tgsi_instruction[] =
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
[TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE,
tgsi_trans_srcx_replicate},
[TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE,
tgsi_trans_srcx_replicate},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
+ [33] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
[TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
[TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
[TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /*
unconditional kill */
[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
[TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
@@ -9440,21 +9437,21 @@ static const struct r600_shader_tgsi_instruction
cm_shader_tgsi_instruction[] =
[23] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
[TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
[TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
[TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
[TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
[TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
+ [33] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
[TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
[TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
[TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /*
unconditional kill */
[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
[TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 1966752..0a49bc2 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -760,22 +760,20 @@ static void emit_rsq(const struct lp_build_tgsi_action
*action,
emit_data->output[emit_data->chan] =
lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_DIV,
bld_base->base.one, sqrt);
}
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
{
lp_set_default_actions(bld_base);
- bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
- bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.fabs.f32";
bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
bld_base->op_actions[TGSI_OPCODE_BREV].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
HAVE_LLVM >= 0x0308 ? "llvm.bitreverse.i32" :
"llvm.AMDGPU.brev";
bld_base->op_actions[TGSI_OPCODE_CEIL].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
bld_base->op_actions[TGSI_OPCODE_CLAMP].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name =
diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c
b/src/gallium/drivers/svga/svga_tgsi_insn.c
index 0e20013..47a0afc 100644
--- a/src/gallium/drivers/svga/svga_tgsi_insn.c
+++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
@@ -36,21 +36,20 @@
static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
static unsigned
translate_opcode(uint opcode)
{
switch (opcode) {
- case TGSI_OPCODE_ABS: return SVGA3DOP_ABS;
case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
case TGSI_OPCODE_DP2A: return SVGA3DOP_DP2ADD;
case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 981251a..e7cfb40 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -3449,42 +3449,20 @@ emit_puint_to_sscaled(struct svga_shader_emitter_v10
*emit,
&src_xxxx, &lshift, FALSE);
emit_instruction_op2(emit, VGPU10_OPCODE_ISHR, &tmp_dst,
&tmp_src, &rshift, FALSE);
emit_instruction_op1(emit, VGPU10_OPCODE_ITOF, dst, &tmp_src, FALSE);
free_temp_indexes(emit);
}
/**
- * Emit code for TGSI_OPCODE_ABS instruction.
- */
-static boolean
-emit_abs(struct svga_shader_emitter_v10 *emit,
- const struct tgsi_full_instruction *inst)
-{
- /* dst = ABS(s0):
- * dst = abs(s0)
- * Translates into:
- * MOV dst, abs(s0)
- */
- struct tgsi_full_src_register abs_src0 = absolute_src(&inst->Src[0]);
-
- /* MOV dst, abs(s0) */
- emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
- &abs_src0, inst->Instruction.Saturate);
-
- return TRUE;
-}
-
-
-/**
* Emit code for TGSI_OPCODE_ARL or TGSI_OPCODE_UARL instruction.
*/
static boolean
emit_arl_uarl(struct svga_shader_emitter_v10 *emit,
const struct tgsi_full_instruction *inst)
{
unsigned index = inst->Dst[0].Register.Index;
struct tgsi_full_dst_register dst;
unsigned opcode;
@@ -5749,22 +5727,20 @@ emit_vgpu10_instruction(struct svga_shader_emitter_v10
*emit,
case TGSI_OPCODE_XOR:
/* simple instructions */
return emit_simple(emit, inst);
case TGSI_OPCODE_MOV:
return emit_mov(emit, inst);
case TGSI_OPCODE_EMIT:
return emit_vertex(emit, inst);
case TGSI_OPCODE_ENDPRIM:
return emit_endprim(emit, inst);
- case TGSI_OPCODE_ABS:
- return emit_abs(emit, inst);
case TGSI_OPCODE_IABS:
return emit_iabs(emit, inst);
case TGSI_OPCODE_ARL:
/* fall-through */
case TGSI_OPCODE_UARL:
return emit_arl_uarl(emit, inst);
case TGSI_OPCODE_BGNSUB:
/* no-op */
return TRUE;
case TGSI_OPCODE_CAL:
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index ee59df0..3538090 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -354,21 +354,21 @@ struct tgsi_property_data {
#define TGSI_OPCODE_F2I64 23
#define TGSI_OPCODE_FRC 24
#define TGSI_OPCODE_CLAMP 25
#define TGSI_OPCODE_FLR 26
#define TGSI_OPCODE_ROUND 27
#define TGSI_OPCODE_EX2 28
#define TGSI_OPCODE_LG2 29
#define TGSI_OPCODE_POW 30
#define TGSI_OPCODE_XPD 31
#define TGSI_OPCODE_U2I64 32
-#define TGSI_OPCODE_ABS 33
+/* gap */
#define TGSI_OPCODE_I2I64 34
#define TGSI_OPCODE_DPH 35
#define TGSI_OPCODE_COS 36
#define TGSI_OPCODE_DDX 37
#define TGSI_OPCODE_DDY 38
#define TGSI_OPCODE_KILL 39 /* unconditional */
#define TGSI_OPCODE_PK2H 40
#define TGSI_OPCODE_PK2US 41
#define TGSI_OPCODE_PK4B 42
#define TGSI_OPCODE_PK4UB 43
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 9599296..1be1f6c 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -91,100 +91,113 @@ static int swizzle_for_type(const glsl_type *type, int
component = 0)
class st_src_reg {
public:
st_src_reg(gl_register_file file, int index, const glsl_type *type,
int component = 0, unsigned array_id = 0)
{
assert(file != PROGRAM_ARRAY || array_id != 0);
this->file = file;
this->index = index;
this->swizzle = swizzle_for_type(type, component);
this->negate = 0;
+ this->abs = 0;
this->index2D = 0;
this->type = type ? type->base_type : GLSL_TYPE_ERROR;
this->reladdr = NULL;
this->reladdr2 = NULL;
this->has_index2 = false;
this->double_reg2 = false;
this->array_id = array_id;
this->is_double_vertex_input = false;
}
st_src_reg(gl_register_file file, int index, enum glsl_base_type type)
{
assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
this->type = type;
this->file = file;
this->index = index;
this->index2D = 0;
this->swizzle = SWIZZLE_XYZW;
this->negate = 0;
+ this->abs = 0;
this->reladdr = NULL;
this->reladdr2 = NULL;
this->has_index2 = false;
this->double_reg2 = false;
this->array_id = 0;
this->is_double_vertex_input = false;
}
st_src_reg(gl_register_file file, int index, enum glsl_base_type type, int
index2D)
{
assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
this->type = type;
this->file = file;
this->index = index;
this->index2D = index2D;
this->swizzle = SWIZZLE_XYZW;
this->negate = 0;
+ this->abs = 0;
this->reladdr = NULL;
this->reladdr2 = NULL;
this->has_index2 = false;
this->double_reg2 = false;
this->array_id = 0;
this->is_double_vertex_input = false;
}
st_src_reg()
{
this->type = GLSL_TYPE_ERROR;
this->file = PROGRAM_UNDEFINED;
this->index = 0;
this->index2D = 0;
this->swizzle = 0;
this->negate = 0;
+ this->abs = 0;
this->reladdr = NULL;
this->reladdr2 = NULL;
this->has_index2 = false;
this->double_reg2 = false;
this->array_id = 0;
this->is_double_vertex_input = false;
}
explicit st_src_reg(st_dst_reg reg);
int16_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
int16_t index2D;
uint16_t swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
int negate:4; /**< NEGATE_XYZW mask from mesa */
+ unsigned abs:1;
enum glsl_base_type type:4; /** GLSL_TYPE_* from GLSL IR (enum
glsl_base_type) */
unsigned has_index2:1;
gl_register_file file:5; /**< PROGRAM_* from Mesa */
/*
* Is this the second half of a double register pair?
* currently used for input mapping only.
*/
unsigned double_reg2:1;
unsigned is_double_vertex_input:1;
unsigned array_id:10;
/** Register index should be offset by the integer in this reg. */
st_src_reg *reladdr;
st_src_reg *reladdr2;
+
+ st_src_reg get_abs()
+ {
+ st_src_reg reg = *this;
+ reg.negate = 0;
+ reg.abs = 1;
+ return reg;
+ }
};
class st_dst_reg {
public:
st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type,
int index)
{
assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
this->file = file;
this->index = index;
this->index2D = 0;
@@ -238,20 +251,21 @@ public:
st_src_reg *reladdr2;
};
st_src_reg::st_src_reg(st_dst_reg reg)
{
this->type = reg.type;
this->file = reg.file;
this->index = reg.index;
this->swizzle = SWIZZLE_XYZW;
this->negate = 0;
+ this->abs = 0;
this->reladdr = reg.reladdr;
this->index2D = reg.index2D;
this->reladdr2 = reg.reladdr2;
this->has_index2 = reg.has_index2;
this->double_reg2 = false;
this->array_id = reg.array_id;
this->is_double_vertex_input = false;
}
st_dst_reg::st_dst_reg(st_src_reg reg)
@@ -947,21 +961,20 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op,
case2iu(MOD, UMOD);
casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ);
casecomp(SNE, FSNE, USNE, USNE, DSNE);
casecomp(SGE, FSGE, ISGE, USGE, DSGE);
casecomp(SLT, FSLT, ISLT, USLT, DSLT);
case2iu(ISHR, USHR);
case3fid(SSG, ISSG, DSSG);
- case3fid(ABS, IABS, DABS);
case2iu(IBFE, UBFE);
case2iu(IMSB, UMSB);
case2iu(IMUL_HI, UMUL_HI);
case3fid(SQRT, SQRT, DSQRT);
case3fid(RCP, RCP, DRCP);
case3fid(RSQ, RSQ, DRSQ);
@@ -1221,20 +1234,21 @@ type_has_array_or_matrix(const glsl_type *type)
* storage).
*/
st_src_reg
glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
{
st_src_reg src;
src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
src.reladdr = NULL;
src.negate = 0;
+ src.abs = 0;
if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
if (next_array >= max_num_arrays) {
max_num_arrays += 32;
array_sizes = (unsigned*)
realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
}
src.file = PROGRAM_ARRAY;
src.index = 0;
@@ -1586,21 +1600,26 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression*
ir, st_src_reg *op)
emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
else {
op[0].negate = ~op[0].negate;
result_src = op[0];
}
break;
case ir_unop_subroutine_to_int:
emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
break;
case ir_unop_abs:
- emit_asm(ir, TGSI_OPCODE_ABS, result_dst, op[0]);
+ if (result_dst.type == GLSL_TYPE_FLOAT)
+ emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
+ else if (result_dst.type == GLSL_TYPE_DOUBLE)
+ emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
+ else
+ emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
break;
case ir_unop_sign:
emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
break;
case ir_unop_rcp:
emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
break;
case ir_unop_exp2:
emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
@@ -1912,22 +1931,21 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression*
ir, st_src_reg *op)
case ir_unop_sqrt:
if (have_sqrt) {
emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
} else {
/* This is the only instruction sequence that makes the game "Risen"
* render correctly. ABS is not required for the game, but since GLSL
* declares negative values as "undefined", allowing us to do whatever
* we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
* behavior.
*/
- emit_scalar(ir, TGSI_OPCODE_ABS, result_dst, op[0]);
- emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, result_src);
+ emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
}
break;
case ir_unop_rsq:
emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
break;
case ir_unop_i2f:
if (native_integers) {
emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
break;
@@ -1967,21 +1985,21 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression*
ir, st_src_reg *op)
break;
case ir_unop_f2u:
if (native_integers)
emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
else
emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
break;
case ir_unop_bitcast_f2i:
case ir_unop_bitcast_f2u:
/* Make sure we don't propagate the negate modifier to integer opcodes.
*/
- if (op[0].negate)
+ if (op[0].negate || op[0].abs)
emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
else
result_src = op[0];
result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
GLSL_TYPE_UINT;
break;
case ir_unop_bitcast_i2f:
case ir_unop_bitcast_u2f:
result_src = op[0];
result_src.type = GLSL_TYPE_FLOAT;
@@ -2069,20 +2087,21 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression*
ir, st_src_reg *op)
unsigned const_offset = const_offset_ir ? const_offset_ir->value.u[0] :
0;
unsigned const_block = const_uniform_block ?
const_uniform_block->value.u[0] + 1 : 0;
st_src_reg index_reg = get_temp(glsl_type::uint_type);
st_src_reg cbuf;
cbuf.type = ir->type->base_type;
cbuf.file = PROGRAM_CONSTANT;
cbuf.index = 0;
cbuf.reladdr = NULL;
cbuf.negate = 0;
+ cbuf.abs = 0;
assert(ir->type->is_vector() || ir->type->is_scalar());
if (const_offset_ir) {
/* Constant index into constant buffer */
cbuf.reladdr = NULL;
cbuf.index = const_offset / 16;
}
else {
ir_expression *offset_expr = ir->operands[1]->as_expression();
@@ -4836,21 +4855,22 @@ glsl_to_tgsi_visitor::copy_propagate(void)
if (inst->op == TGSI_OPCODE_MOV &&
inst->dst[0].file == PROGRAM_TEMPORARY &&
!(inst->dst[0].file == inst->src[0].file &&
inst->dst[0].index == inst->src[0].index) &&
!inst->dst[0].reladdr &&
!inst->dst[0].reladdr2 &&
!inst->saturate &&
inst->src[0].file != PROGRAM_ARRAY &&
!inst->src[0].reladdr &&
!inst->src[0].reladdr2 &&
- !inst->src[0].negate) {
+ !inst->src[0].negate &&
+ !inst->src[0].abs) {
for (int i = 0; i < 4; i++) {
if (inst->dst[0].writemask & (1 << i)) {
acp[4 * inst->dst[0].index + i] = inst;
acp_level[4 * inst->dst[0].index + i] = level;
}
}
}
}
ralloc_free(acp_level);
@@ -5509,20 +5529,23 @@ translate_src(struct st_translate *t, const st_src_reg
*src_reg)
else
src = ureg_src_dimension(src, src_reg->index2D);
}
src = ureg_swizzle(src,
GET_SWZ(src_reg->swizzle, 0) & 0x3,
GET_SWZ(src_reg->swizzle, 1) & 0x3,
GET_SWZ(src_reg->swizzle, 2) & 0x3,
GET_SWZ(src_reg->swizzle, 3) & 0x3);
+ if (src_reg->abs)
+ src = ureg_abs(src);
+
if ((src_reg->negate & 0xf) == NEGATE_XYZW)
src = ureg_negate(src);
if (src_reg->reladdr != NULL) {
assert(src_reg->file != PROGRAM_TEMPORARY);
src = ureg_src_indirect(src, ureg_src(t->address[0]));
}
return src;
}
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index 0a225ae..1768356 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -420,22 +420,20 @@ static void emit_swz( struct st_translate *t,
#undef IMM_NEG_ONE
}
static unsigned
translate_opcode( unsigned op )
{
switch( op ) {
case OPCODE_ARL:
return TGSI_OPCODE_ARL;
- case OPCODE_ABS:
- return TGSI_OPCODE_ABS;
case OPCODE_ADD:
return TGSI_OPCODE_ADD;
case OPCODE_CMP:
return TGSI_OPCODE_CMP;
case OPCODE_COS:
return TGSI_OPCODE_COS;
case OPCODE_DP3:
return TGSI_OPCODE_DP3;
case OPCODE_DP4:
return TGSI_OPCODE_DP4;
@@ -557,20 +555,24 @@ compile_instruction(
ureg_insn( ureg,
translate_opcode( inst->Opcode ),
dst, num_dst,
src, num_src );
break;
case OPCODE_RSQ:
ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
break;
+ case OPCODE_ABS:
+ ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
+ break;
+
default:
ureg_insn( ureg,
translate_opcode( inst->Opcode ),
dst, num_dst,
src, num_src );
break;
}
}
--
2.7.4
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