[Mesa-dev] [PATCH 44/50] i965: Add support for constant evaluation on Q and UQ types

[Ian Romanick]

From: Ian Romanick <ian.d.roman...@intel.com>

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_reg.h      |  1 +
 src/mesa/drivers/dri/i965/brw_shader.cpp | 26 +++++++++++++++++++-------
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_reg.h 
b/src/mesa/drivers/dri/i965/brw_reg.h
index 8907c9c..8419c0a 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -264,6 +264,7 @@ struct brw_reg {
 
       double df;
       uint64_t u64;
+      int64_t d64;
       float f;
       int   d;
       unsigned ud;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 63eb42a..bde3355 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -65,12 +65,14 @@ brw_type_for_base_type(const struct glsl_type *type)
       return BRW_REGISTER_TYPE_UD;
    case GLSL_TYPE_DOUBLE:
       return BRW_REGISTER_TYPE_DF;
+   case GLSL_TYPE_UINT64:
+      return BRW_REGISTER_TYPE_UQ;
+   case GLSL_TYPE_INT64:
+      return BRW_REGISTER_TYPE_Q;
    case GLSL_TYPE_VOID:
    case GLSL_TYPE_ERROR:
    case GLSL_TYPE_INTERFACE:
    case GLSL_TYPE_FUNCTION:
-   case GLSL_TYPE_UINT64:
-   case GLSL_TYPE_INT64:
       unreachable("not reached");
    }
 
@@ -546,15 +548,16 @@ brw_negate_immediate(enum brw_reg_type type, struct 
brw_reg *reg)
    case BRW_REGISTER_TYPE_DF:
       reg->df = -reg->df;
       return true;
+   case BRW_REGISTER_TYPE_UQ:
+   case BRW_REGISTER_TYPE_Q:
+      reg->d64 = -reg->d64;
+      return true;
    case BRW_REGISTER_TYPE_UB:
    case BRW_REGISTER_TYPE_B:
       unreachable("no UB/B immediates");
    case BRW_REGISTER_TYPE_UV:
    case BRW_REGISTER_TYPE_V:
       assert(!"unimplemented: negate UV/V immediate");
-   case BRW_REGISTER_TYPE_UQ:
-   case BRW_REGISTER_TYPE_Q:
-      assert(!"unimplemented: negate UQ/Q immediate");
    case BRW_REGISTER_TYPE_HF:
       assert(!"unimplemented: negate HF immediate");
    }
@@ -581,6 +584,9 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg 
*reg)
    case BRW_REGISTER_TYPE_VF:
       reg->ud &= ~0x80808080;
       return true;
+   case BRW_REGISTER_TYPE_Q:
+      reg->d64 = imaxabs(reg->d64);
+      return true;
    case BRW_REGISTER_TYPE_UB:
    case BRW_REGISTER_TYPE_B:
       unreachable("no UB/B immediates");
@@ -594,8 +600,6 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg 
*reg)
       assert(!"unimplemented: abs unsigned immediate");
    case BRW_REGISTER_TYPE_V:
       assert(!"unimplemented: abs V immediate");
-   case BRW_REGISTER_TYPE_Q:
-      assert(!"unimplemented: abs Q immediate");
    case BRW_REGISTER_TYPE_HF:
       assert(!"unimplemented: abs HF immediate");
    }
@@ -723,6 +727,9 @@ backend_reg::is_zero() const
    case BRW_REGISTER_TYPE_D:
    case BRW_REGISTER_TYPE_UD:
       return d == 0;
+   case BRW_REGISTER_TYPE_UQ:
+   case BRW_REGISTER_TYPE_Q:
+      return u64 == 0;
    default:
       return false;
    }
@@ -742,6 +749,9 @@ backend_reg::is_one() const
    case BRW_REGISTER_TYPE_D:
    case BRW_REGISTER_TYPE_UD:
       return d == 1;
+   case BRW_REGISTER_TYPE_UQ:
+   case BRW_REGISTER_TYPE_Q:
+      return u64 == 1;
    default:
       return false;
    }
@@ -760,6 +770,8 @@ backend_reg::is_negative_one() const
       return df == -1.0;
    case BRW_REGISTER_TYPE_D:
       return d == -1;
+   case BRW_REGISTER_TYPE_Q:
+      return d64 == -1;
    default:
       return false;
    }
-- 
2.7.4

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