[Mesa-dev] [PATCH 2/2] gm107/ir: optimize 32-bit CONST load to mov

[Samuel Pitoiset]

This is not allowed for indirect accesses because the source
GPR might be erased by a subsequent instruction (WaR hazard)
if we don't emit a read dep bar.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
 .../drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp   | 16 ++++++++++++++++
 .../drivers/nouveau/codegen/nv50_ir_lowering_gm107.h     |  1 +
 2 files changed, 17 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
index ead6f9e..2c0e8de 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -61,6 +61,19 @@ GM107LegalizeSSA::handlePFETCH(Instruction *i)
    i->setSrc(1, NULL);
 }
 
+void
+GM107LegalizeSSA::handleLOAD(Instruction *i)
+{
+   if (i->src(0).getFile() != FILE_MEMORY_CONST)
+      return;
+   if (i->src(0).isIndirect(0))
+      return;
+   if (typeSizeof(i->dType) != 4)
+      return;
+
+   i->op = OP_MOV;
+}
+
 bool
 GM107LegalizeSSA::visit(Instruction *i)
 {
@@ -68,6 +81,9 @@ GM107LegalizeSSA::visit(Instruction *i)
    case OP_PFETCH:
       handlePFETCH(i);
       break;
+   case OP_LOAD:
+      handleLOAD(i);
+      break;
    default:
       break;
    }
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
index 8cac76f..f51c2bb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
@@ -22,6 +22,7 @@ private:
    virtual bool visit(Instruction *);
 
    void handlePFETCH(Instruction *);
+   void handleLOAD(Instruction *);
 
    struct BarUse {
       BarUse(Instruction *use, const Instruction *bar)
-- 
2.10.1

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