This series adds the core "Register Region Restrictions" to the shader validator. I've added a make check test to verify that the validation checks are correct.
There is still quite a bit more to do, but the next section in the PRM is "Special Requirements for Handling Double Precision Data Types" and I thought it would be mean to do so without reviewing Igalia's Gen7 FP64 work first :) [PATCH 01/18] gtest: Update to 1.8.0. [PATCH 02/18] i965: Use W-typed immediate in brw_F32TO16(). [PATCH 03/18] i965/vec4: Use UW-typed operands when dest is UW. [PATCH 04/18] i965: Mark error annotation on correct SIMD16 inst. [PATCH 05/18] i965: Make ERROR_IF usable from other functions. [PATCH 06/18] i965: Add a CHECK macro to call more complicated [PATCH 07/18] i965: Add a test for the EU assembly validator. [PATCH 08/18] i965: Structure code so unsupported inst will not [PATCH 09/18] i965: Simplify num_sources_from_inst(). [PATCH 10/18] i965: Factor out sources_not_null() validation [PATCH 11/18] i965: Factor out send_restrictions() function. [PATCH 12/18] i965: Claim that SEND/math has two sources. [PATCH 13/18] i965: Validate math instruction sources. [PATCH 14/18] i965: Replace reg_type_size[] with a function. [PATCH 15/18] i965: Validate "General Restrictions on Regioning [PATCH 16/18] i965: Validate "General Restrictions Based on Operand [PATCH 17/18] i965: Validate "Region Alignment Rules" [PATCH 18/18] i965: Validate "Special Cases for Byte Operations" _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
