On Nov 19, 2016 6:56 PM, "Jordan Justen" <jordan.l.jus...@intel.com> wrote:
>
> On 2016-11-19 15:08:11, Jason Ekstrand wrote:
> > Fixes 61 Vulkan CTS tests on Haswell
> >
> > Cc: "13.0" <mesa-sta...@lists.freedesktop.org>
> > ---
> > src/intel/vulkan/anv_genX.h | 2 ++
> > src/intel/vulkan/genX_blorp_exec.c | 2 ++
> > src/intel/vulkan/genX_cmd_buffer.c | 31 +++++++++++++++++++++++++++++++
> > 3 files changed, 35 insertions(+)
> >
> > diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h
> > index 7937170..296b1ae 100644
> > --- a/src/intel/vulkan/anv_genX.h
> > +++ b/src/intel/vulkan/anv_genX.h
> > @@ -42,6 +42,8 @@ void genX(cmd_buffer_emit_state_base_address)(struct
anv_cmd_buffer *cmd_buffer)
> >
> > void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer
*cmd_buffer);
> >
> > +void genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer
*cmd_buffer);
> > +
> > void genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer);
> > void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer
*cmd_buffer);
> >
> > diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
> > index a705de0..721b6e5 100644
> > --- a/src/intel/vulkan/genX_blorp_exec.c
> > +++ b/src/intel/vulkan/genX_blorp_exec.c
> > @@ -150,6 +150,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
> >
> > genX(flush_pipeline_select_3d)(cmd_buffer);
> >
> > + genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
> > +
> > blorp_exec(batch, params);
> >
> > cmd_buffer->state.vb_dirty = ~0;
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
> > index 985bae0..b873a69 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -1978,6 +1978,35 @@ genX(flush_pipeline_select_gpgpu)(struct
anv_cmd_buffer *cmd_buffer)
> > }
> > }
> >
> > +void
> > +genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer
*cmd_buffer)
> > +{
> > + if (GEN_GEN > 7)
>
> Should it be?
>
> if (!GEN_IS_HASWELL)
I thought it applied to ivy bridge as well
> Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
>
> > + return;
> > +
> > + /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
> > + *
> > + * "Restriction: Prior to changing Depth/Stencil Buffer state
(i.e., any
> > + * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
> > + * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must
first
> > + * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall
bit
> > + * set), followed by a pipelined depth cache flush (PIPE_CONTROL
with
> > + * Depth Flush Bit set, followed by another pipelined depth stall
> > + * (PIPE_CONTROL with Depth Stall Bit set), unless SW can
otherwise
> > + * guarantee that the pipeline from WM onwards is already
flushed (e.g.,
> > + * via a preceding MI_FLUSH)."
> > + */
> > + anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
> > + pipe.DepthStallEnable = true;
> > + }
> > + anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
> > + pipe.DepthCacheFlushEnable = true;
> > + }
> > + anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
> > + pipe.DepthStallEnable = true;
> > + }
> > +}
> > +
> > static void
> > cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
> > {
> > @@ -1994,6 +2023,8 @@ cmd_buffer_emit_depth_stencil(struct
anv_cmd_buffer *cmd_buffer)
> > /* FIXME: Implement the PMA stall W/A */
> > /* FIXME: Width and Height are wrong */
> >
> > + genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
> > +
> > /* Emit 3DSTATE_DEPTH_BUFFER */
> > if (has_depth) {
> > anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
db) {
> > --
> > 2.5.0.400.gff86faf
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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