Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
On Mon, Sep 26, 2016 at 5:10 PM, Nanley Chery <nanleych...@gmail.com> wrote:
> From: Chad Versace <chad.vers...@intel.com>
>
> Nanley Chery:
> (rebase)
> - Resolve conflicts with new anv_batch_emit macro
> (amend)
> - Handle a QPitch TODO
> - Emit 3DSTATE_HIER_DEPTH_BUFFER on pre-BDW systems
> - Only use HiZ for single-subpass renderpasses
> - Emit the HiZ instruction before the stencil instruction to follow the
> optimized clear sequence specified in the PRMs
> - Don't modify clear params
> - Enable resolves when a HiZ buffer is used to ensure depth buffer
> validity
>
> Provides an FPS increase of ~15% on the Sascha triangle and multisampling
> demos.
>
> Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
>
> ---
>
> v2: Emit zero'ed 3DSTATE_HIER_DEPTH_BUFFER when hiz is disabled
> (Jason, Chad)
>
> src/intel/vulkan/gen8_cmd_buffer.c | 4 ++++
> src/intel/vulkan/genX_cmd_buffer.c | 43 ++++++++++++++++++++++++++++++
> ++++----
> 2 files changed, 43 insertions(+), 4 deletions(-)
>
> diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
> b/src/intel/vulkan/gen8_cmd_buffer.c
> index a13413c..14e6a7b 100644
> --- a/src/intel/vulkan/gen8_cmd_buffer.c
> +++ b/src/intel/vulkan/gen8_cmd_buffer.c
> @@ -417,6 +417,10 @@ genX(cmd_buffer_do_hz_op)(struct anv_cmd_buffer
> *cmd_buffer,
> if (iview == NULL || !anv_image_has_hiz(iview->image))
> return;
>
> + /* FIXME: Implement multi-subpass HiZ */
> + if (cmd_buffer->state.pass->subpass_count > 1)
> + return;
> +
> const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
> const bool full_surface_op =
> cmd_state->render_area.extent.width == iview->extent.width
> &&
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 6a84383..2cb1539 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -1199,6 +1199,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
> *cmd_buffer)
> anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
> const struct anv_image *image = iview ? iview->image : NULL;
> const bool has_depth = image && (image->aspects &
> VK_IMAGE_ASPECT_DEPTH_BIT);
> + const bool has_hiz = image != NULL && anv_image_has_hiz(image);
> const bool has_stencil =
> image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
>
> @@ -1211,7 +1212,12 @@ cmd_buffer_emit_depth_stencil(struct
> anv_cmd_buffer *cmd_buffer)
> db.SurfaceType = SURFTYPE_2D;
> db.DepthWriteEnable = true;
> db.StencilWriteEnable = has_stencil;
> - db.HierarchicalDepthBufferEnable = false;
> +
> + if (cmd_buffer->state.pass->subpass_count == 1) {
> + db.HierarchicalDepthBufferEnable = has_hiz;
> + } else {
> + anv_finishme("Multiple-subpass HiZ not implemented");
> + }
>
> db.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
>
> &image->depth_surface.isl);
> @@ -1263,6 +1269,36 @@ cmd_buffer_emit_depth_stencil(struct
> anv_cmd_buffer *cmd_buffer)
> }
> }
>
> + if (has_hiz) {
> + anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER),
> hdb) {
> + hdb.HierarchicalDepthBufferObjectControlState = GENX(MOCS);
> + hdb.SurfacePitch = image->hiz_surface.isl.row_pitch - 1;
> + hdb.SurfaceBaseAddress = (struct anv_address) {
> + .bo = image->bo,
> + .offset = image->offset + image->hiz_surface.offset,
> + };
> +#if GEN_GEN >= 8
> + /* From the SKL PRM Vol2a:
> + *
> + * The interpretation of this field is dependent on Surface
> Type
> + * as follows:
> + * - SURFTYPE_1D: distance in pixels between array slices
> + * - SURFTYPE_2D/CUBE: distance in rows between array slices
> + * - SURFTYPE_3D: distance in rows between R - slices
> + *
> + * ISL implements HiZ surfaces for 1D depth buffers as 2D.
> Therefore
> + * the depth buffer needs to be checked for the dimension.
> + */
> + hdb.SurfaceQPitch =
> + image->depth_surface.isl.dim == ISL_SURF_DIM_1D ?
> + isl_surf_get_array_pitch_el(&image->hiz_surface.isl) >> 2
> :
> + isl_surf_get_array_pitch_el_rows(&image->hiz_surface.isl)
> >> 2;
> +#endif
> + }
> + } else {
> + anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER),
> hdb);
> + }
> +
> /* Emit 3DSTATE_STENCIL_BUFFER */
> if (has_stencil) {
> anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
> sb) {
> @@ -1285,9 +1321,6 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
> *cmd_buffer)
> anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
> sb);
> }
>
> - /* Disable hierarchial depth buffers. */
> - anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER),
> hz);
> -
> /* Clear the clear params. */
> anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS), cp);
> }
> @@ -1323,6 +1356,7 @@ void genX(CmdBeginRenderPass)(
> genX(flush_pipeline_select_3d)(cmd_buffer);
>
> genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
> + genX(cmd_buffer_do_hz_op)(cmd_buffer, BLORP_HIZ_OP_HIZ_RESOLVE);
> anv_cmd_buffer_clear_subpass(cmd_buffer);
> }
>
> @@ -1344,6 +1378,7 @@ void genX(CmdEndRenderPass)(
> {
> ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
>
> + genX(cmd_buffer_do_hz_op)(cmd_buffer, BLORP_HIZ_OP_DEPTH_RESOLVE);
> anv_cmd_buffer_resolve_subpass(cmd_buffer);
>
> #ifndef NDEBUG
> --
> 2.10.0
>
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