From: Nicolai Hähnle <nicolai.haeh...@amd.com>
These functions extract the pipe state structure from the current
descriptors, for state saving.
---
src/gallium/drivers/radeonsi/si_descriptors.c | 46 +++++++++++++++++++++++++++
src/gallium/drivers/radeonsi/si_state.h | 5 +++
2 files changed, 51 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index b1a8594..d82910c 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -830,20 +830,41 @@ static void si_buffer_resources_begin_new_cs(struct
si_context *sctx,
/* Add buffers to the CS. */
while (mask) {
int i = u_bit_scan(&mask);
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct
r600_resource*)buffers->buffers[i],
buffers->shader_usage, buffers->priority);
}
}
+static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
+ struct si_descriptors *descs,
+ unsigned idx, struct pipe_resource
**buf,
+ unsigned *offset, unsigned *size)
+{
+ pipe_resource_reference(buf, buffers->buffers[idx]);
+ if (*buf) {
+ struct r600_resource *res = (struct r600_resource *)buf;
+ const uint32_t *desc = descs->list + idx * 4;
+ uint64_t va;
+
+ *size = desc[2];
+
+ assert(G_008F04_STRIDE(desc[1]) == 0);
+ va = ((uint64_t)desc[1] << 32) | desc[0];
+
+ assert(va >= res->gpu_address && va + *size <= res->gpu_address
+ res->bo_size);
+ *offset = va - res->gpu_address;
+ }
+}
+
/* VERTEX BUFFERS */
static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
{
struct si_descriptors *desc = &sctx->vertex_buffers;
int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
int i;
for (i = 0; i < count; i++) {
int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
@@ -1055,20 +1076,30 @@ static void si_pipe_set_constant_buffer(struct
pipe_context *ctx,
struct si_context *sctx = (struct si_context *)ctx;
if (shader >= SI_NUM_SHADERS)
return;
si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
si_const_buffer_descriptors_idx(shader),
slot, input);
}
+void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
+ uint slot, struct pipe_constant_buffer *cbuf)
+{
+ cbuf->user_buffer = NULL;
+ si_get_buffer_from_descriptors(
+ &sctx->const_buffers[shader],
+ si_const_buffer_descriptors(sctx, shader),
+ slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
+}
+
/* SHADER BUFFERS */
static unsigned
si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
{
return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
SI_SHADER_DESCS_SHADER_BUFFERS;
}
static struct si_descriptors *
@@ -1125,20 +1156,35 @@ static void si_set_shader_buffers(struct pipe_context
*ctx,
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
buffers->shader_usage,
buffers->priority, true);
buffers->enabled_mask |= 1u << slot;
descs->dirty_mask |= 1u << slot;
sctx->descriptors_dirty |=
1u << si_shader_buffer_descriptors_idx(shader);
}
}
+void si_get_shader_buffers(struct si_context *sctx, uint shader,
+ uint start_slot, uint count,
+ struct pipe_shader_buffer *sbuf)
+{
+ struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
+ struct si_descriptors *descs = si_shader_buffer_descriptors(sctx,
shader);
+
+ for (unsigned i = 0; i < count; ++i) {
+ si_get_buffer_from_descriptors(
+ buffers, descs, start_slot + i,
+ &sbuf[i].buffer, &sbuf[i].buffer_offset,
+ &sbuf[i].buffer_size);
+ }
+}
+
/* RING BUFFERS */
void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
struct pipe_resource *buffer,
unsigned stride, unsigned num_records,
bool add_tid, bool swizzle,
unsigned element_size, unsigned index_stride, uint64_t
offset)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_buffer_resources *buffers = &sctx->rw_buffers;
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index e83b428..3ebf578 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -274,20 +274,25 @@ struct si_buffer_resources {
} while(0)
/* si_descriptors.c */
void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
void si_ce_enable_loads(struct radeon_winsys_cs *ib);
void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
const struct radeon_surf_level
*base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state);
+void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
+ uint slot, struct pipe_constant_buffer *cbuf);
+void si_get_shader_buffers(struct si_context *sctx, uint shader,
+ uint start_slot, uint count,
+ struct pipe_shader_buffer *sbuf);
void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
struct pipe_resource *buffer,
unsigned stride, unsigned num_records,
bool add_tid, bool swizzle,
unsigned element_size, unsigned index_stride, uint64_t
offset);
void si_init_all_descriptors(struct si_context *sctx);
bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
