Later we will pass compiler to nir_optimise to be used by the loop unroll
pass.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 ++++------
src/mesa/drivers/dri/i965/brw_nir.c | 7 ++++---
src/mesa/drivers/dri/i965/brw_nir.h | 4 ++--
src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 ++---
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 5 ++---
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 4 ++--
7 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 75642d3..779c098 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -6554,8 +6554,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void
*log_data,
char **error_str)
{
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
- shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
- true);
+ shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true);
brw_nir_set_default_interpolation(compiler->devinfo, shader,
key->flat_shade, key->persample_interp);
brw_nir_lower_fs_inputs(shader);
@@ -6563,7 +6562,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void
*log_data,
if (!key->multisample_fbo)
NIR_PASS_V(shader, demote_sample_qualifiers);
NIR_PASS_V(shader, move_interpolation_to_top);
- shader = brw_postprocess_nir(shader, compiler->devinfo, true);
+ shader = brw_postprocess_nir(shader, compiler, true);
/* key->alpha_test_func means simulating alpha testing via discards,
* so the shader definitely kills pixels.
@@ -6786,8 +6785,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
char **error_str)
{
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
- shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
- true);
+ shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true);
brw_nir_lower_cs_shared(shader);
prog_data->base.total_shared += shader->num_shared;
@@ -6800,7 +6798,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
(unsigned)4 * (prog_data->thread_local_id_index + 1));
brw_nir_lower_intrinsics(shader, &prog_data->base);
- shader = brw_postprocess_nir(shader, compiler->devinfo, true);
+ shader = brw_postprocess_nir(shader, compiler, true);
prog_data->local_size[0] = shader->info.cs.local_size[0];
prog_data->local_size[1] = shader->info.cs.local_size[1];
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index af646ed..0c15b55 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -481,10 +481,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler,
nir_shader *nir)
* will not work.
*/
nir_shader *
-brw_postprocess_nir(nir_shader *nir,
- const struct gen_device_info *devinfo,
+brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
bool is_scalar)
{
+ const struct gen_device_info *devinfo = compiler->devinfo;
bool debug_enabled =
(INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
@@ -546,10 +546,11 @@ brw_postprocess_nir(nir_shader *nir,
nir_shader *
brw_nir_apply_sampler_key(nir_shader *nir,
- const struct gen_device_info *devinfo,
+ const struct brw_compiler *compiler,
const struct brw_sampler_prog_key_data *key_tex,
bool is_scalar)
{
+ const struct gen_device_info *devinfo = compiler->devinfo;
nir_lower_tex_options tex_options = { 0 };
/* Iron Lake and prior require lowering of all rectangle textures */
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h
b/src/mesa/drivers/dri/i965/brw_nir.h
index b025d55..4af22fd 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -113,7 +113,7 @@ void brw_nir_lower_fs_outputs(nir_shader *nir);
void brw_nir_lower_cs_shared(nir_shader *nir);
nir_shader *brw_postprocess_nir(nir_shader *nir,
- const struct gen_device_info *devinfo,
+ const struct brw_compiler *compiler,
bool is_scalar);
bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
@@ -125,7 +125,7 @@ bool brw_nir_apply_trig_workarounds(nir_shader *nir);
void brw_nir_apply_tcs_quads_workaround(nir_shader *nir);
nir_shader *brw_nir_apply_sampler_key(nir_shader *nir,
- const struct gen_device_info *devinfo,
+ const struct brw_compiler *compiler,
const struct brw_sampler_prog_key_data
*key,
bool is_scalar);
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index ea39252..863056f 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1336,10 +1336,10 @@ brw_compile_tes(const struct brw_compiler *compiler,
nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
nir->info.patch_inputs_read);
- nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
+ nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
brw_nir_lower_tes_inputs(nir, &input_vue_map);
brw_nir_lower_vue_outputs(nir, is_scalar);
- nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
+ nir = brw_postprocess_nir(nir, compiler, is_scalar);
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
nir->info.outputs_written,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index d52fdc0..cf3e948 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2079,12 +2079,11 @@ brw_compile_vs(const struct brw_compiler *compiler,
void *log_data,
{
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
- shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
- is_scalar);
+ shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, is_scalar);
brw_nir_lower_vs_inputs(shader, compiler->devinfo, is_scalar,
use_legacy_snorm_formula, key->gl_attrib_wa_flags);
brw_nir_lower_vue_outputs(shader, is_scalar);
- shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
+ shader = brw_postprocess_nir(shader, compiler, is_scalar);
const unsigned *assembly = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index c5886d4..428fe5a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -616,11 +616,10 @@ brw_compile_gs(const struct brw_compiler *compiler, void
*log_data,
&c.input_vue_map, inputs_read,
shader->info.separate_shader);
- shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
- is_scalar);
+ shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, is_scalar);
brw_nir_lower_vue_inputs(shader, is_scalar, &c.input_vue_map);
brw_nir_lower_vue_outputs(shader, is_scalar);
- shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
+ shader = brw_postprocess_nir(shader, compiler, is_scalar);
prog_data->include_primitive_id =
(shader->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) != 0;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 498fb7c..92dd70c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
@@ -468,13 +468,13 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir->info.outputs_written,
nir->info.patch_outputs_written);
- nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
+ nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map);
if (key->quads_workaround)
brw_nir_apply_tcs_quads_workaround(nir);
- nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
+ nir = brw_postprocess_nir(nir, compiler, is_scalar);
if (is_scalar)
prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 8);
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
