On 08/19/2016 07:11 PM, Marek Olšák wrote:
> From: Ronie Salgado <ronies...@gmail.com>
>
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 18 ++++++++++++++----
> src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 9 +++++++--
> src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 25 +++++++++++++++++++++++++
> 3 files changed, 46 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index b171cc5..bf3e306 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -973,27 +973,37 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
> {
> struct amdgpu_cs *cs = amdgpu_cs(rcs);
> struct amdgpu_winsys *ws = cs->ctx->ws;
> int error_code = 0;
>
> rcs->current.max_dw += amdgpu_cs_epilog_dws(cs->ring_type);
>
> switch (cs->ring_type) {
> case RING_DMA:
> /* pad DMA ring to 8 DWs */
> - while (rcs->current.cdw & 7)
> - OUT_CS(rcs, 0x00000000); /* NOP packet */
> + if (ws->info.chip_class <= SI) {
> + while (rcs->current.cdw & 7)
> + OUT_CS(rcs, 0xf0000000); /* NOP packet */
> + } else {
> + while (rcs->current.cdw & 7)
> + OUT_CS(rcs, 0x00000000); /* NOP packet */
> + }
> break;
> case RING_GFX:
> /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
> - while (rcs->current.cdw & 7)
> - OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
> + if (ws->info.gfx_ib_pad_with_type2) {
> + while (rcs->current.cdw & 7)
> + OUT_CS(rcs, 0x80000000); /* type2 nop packet */
> + } else {
> + while (rcs->current.cdw & 7)
> + OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
> + }
>
> /* Also pad the const IB. */
> if (cs->const_ib.ib_mapped)
> while (!cs->const_ib.base.current.cdw ||
> (cs->const_ib.base.current.cdw & 7))
> OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
>
> if (cs->const_preamble_ib.ib_mapped)
> while (!cs->const_preamble_ib.base.current.cdw ||
> (cs->const_preamble_ib.base.current.cdw & 7))
> OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
> break;
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> index 615d5a2..60c3cb9 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> @@ -119,22 +119,27 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
> addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
> addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
>
> regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
> regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
> regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
>
> regValue.backendDisables = ws->amdinfo.backend_disable[0];
> regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
> regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
> - regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
> - regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
> + if(ws->info.chip_class == SI) {
Trivial style consistency fix 'if(' -> 'if ('.
With that, this series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>
> + regValue.pMacroTileConfig = NULL;
> + regValue.noOfMacroEntries = 0;
> + } else {
> + regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
> + regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
> + }
>
> createFlags.value = 0;
> createFlags.useTileIndex = 1;
> createFlags.degradeBaseLevel = 1;
>
> addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
> addrCreateInput.chipFamily = ws->family;
> addrCreateInput.chipRevision = ws->rev_id;
> addrCreateInput.createFlags = createFlags;
> addrCreateInput.callbacks.allocSysMem = allocSysMem;
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> index d8aed8b..1aa662c 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> @@ -208,35 +208,57 @@ static bool do_winsys_init(struct amdgpu_winsys *ws,
> int fd)
>
> default:
> fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
> goto fail;
> }
>
> if (ws->info.family >= CHIP_TONGA)
> ws->info.chip_class = VI;
> else if (ws->info.family >= CHIP_BONAIRE)
> ws->info.chip_class = CIK;
> + else if(ws->info.family >= CHIP_TAHITI)
> + ws->info.chip_class = SI;
> else {
> fprintf(stderr, "amdgpu: Unknown family.\n");
> goto fail;
> }
>
> /* LLVM 3.6.1 is required for VI. */
> if (ws->info.chip_class >= VI &&
> HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1) {
> fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
> HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
> goto fail;
> }
>
> /* family and rev_id are for addrlib */
> switch (ws->info.family) {
> + case CHIP_TAHITI:
> + ws->family = FAMILY_SI;
> + ws->rev_id = SI_TAHITI_P_A0;
> + break;
> + case CHIP_PITCAIRN:
> + ws->family = FAMILY_SI;
> + ws->rev_id = SI_PITCAIRN_PM_A0;
> + break;
> + case CHIP_VERDE:
> + ws->family = FAMILY_SI;
> + ws->rev_id = SI_CAPEVERDE_M_A0;
> + break;
> + case CHIP_OLAND:
> + ws->family = FAMILY_SI;
> + ws->rev_id = SI_OLAND_M_A0;
> + break;
> + case CHIP_HAINAN:
> + ws->family = FAMILY_SI;
> + ws->rev_id = SI_HAINAN_V_A0;
> + break;
> case CHIP_BONAIRE:
> ws->family = FAMILY_CI;
> ws->rev_id = CI_BONAIRE_M_A0;
> break;
> case CHIP_KAVERI:
> ws->family = FAMILY_KV;
> ws->rev_id = KV_SPECTRE_A0;
> break;
> case CHIP_KABINI:
> ws->family = FAMILY_KV;
> @@ -324,20 +346,23 @@ static bool do_winsys_init(struct amdgpu_winsys *ws,
> int fd)
>
> memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
> sizeof(ws->amdinfo.gb_tile_mode));
> ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
>
> memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
> sizeof(ws->amdinfo.gb_macro_tile_mode));
>
> ws->info.gart_page_size = alignment_info.size_remote;
>
> + if (ws->info.chip_class == SI)
> + ws->info.gfx_ib_pad_with_type2 = TRUE;
> +
> ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") !=
> NULL;
>
> return true;
>
> fail:
> if (ws->addrlib)
> AddrDestroy(ws->addrlib);
> amdgpu_device_deinitialize(ws->dev);
> ws->dev = NULL;
> return false;
>
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