From: Marek Olšák <marek.ol...@amd.com>
Vulkan doesn't do this. The reason may be that CB_COLOR1_INFO.SOURCE_FORMAT
from NI was moved to SPI_SHADER_COL_FORMAT for SI.
I asked CB guys about this 2 days ago and they still haven't replied.
---
src/gallium/drivers/radeonsi/si_state.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 5d55448..a44f977 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2500,27 +2500,20 @@ static void si_emit_framebuffer_state(struct si_context
*sctx, struct r600_atom
radeon_emit(cs, cb_color_fmask); /*
R_028C84_CB_COLOR0_FMASK */
radeon_emit(cs, cb_color_fmask_slice); /*
R_028C88_CB_COLOR0_FMASK_SLICE */
radeon_emit(cs, tex->color_clear_value[0]); /*
R_028C8C_CB_COLOR0_CLEAR_WORD0 */
radeon_emit(cs, tex->color_clear_value[1]); /*
R_028C90_CB_COLOR0_CLEAR_WORD1 */
if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
radeon_emit(cs, ((!tex->dcc_separate_buffer ?
tex->resource.gpu_address : 0) +
tex->dcc_offset +
tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
}
- /* set CB_COLOR1_INFO for possible dual-src blending */
- if (i == 1 && state->cbufs[0] &&
- sctx->framebuffer.dirty_cbufs & (1 << 0)) {
- radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
- cb_color_info);
- i++;
- }
for (; i < 8 ; i++)
if (sctx->framebuffer.dirty_cbufs & (1 << i))
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i
* 0x3C, 0);
/* ZS buffer. */
if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
struct r600_texture *rtex = (struct
r600_texture*)zb->base.texture;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
--
2.7.4
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