Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a65c273..bf32dfd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -4558,6 +4558,18 @@ setup_imm_df(const fs_builder &bld, double v)
if (devinfo->gen >= 8)
return brw_imm_df(v);
+ /* gen7.5 does not support DF immediates straighforward but the DIM
+ * instruction allows to set the 64-bit immediate value.
+ */
+ if (devinfo->is_haswell) {
+ const fs_builder ubld = bld.exec_all();
+ fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1);
+ struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
+ imm.df = v;
+ ubld.DIM(dst, imm);
+ return component(dst, 0);
+ }
+
/* gen7 does not support DF immediates, so we generate a 64-bit constant by
* writing the low 32-bit of the constant to suboffset 0 of a VGRF and
* the high 32-bit to suboffset 4 and then applying a stride of 0.
--
2.7.4
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