On 07/07/16 23:38, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> So far we only used instructions with this size in situations where we >> did not operate per-channel and we wanted to ignore the execution mask, >> but gen7 fp64 will need to emit code with a width of 4 that needs >> normal execution masking. >> --- >> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 1 - >> 1 file changed, 1 deletion(-) >> >> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp >> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp >> index d25d26a..07581d2 100644 >> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp >> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp >> @@ -1649,7 +1649,6 @@ fs_generator::generate_code(const cfg_t *cfg, int >> dispatch_width) >> brw_set_default_acc_write_control(p, inst->writes_accumulator); >> brw_set_default_exec_size(p, cvt(inst->exec_size) - 1); >> >> - assert(inst->force_writemask_all || inst->exec_size >= 8); > > Another possibility would be to relax the assertion to check that > "inst->force_writemask_all || inst->exec_size >= 4" -- Because you can > only control the channel enable group with nibble granularity at best > it's unpractical to split instructions into chunks of execution size > less than four. SIMD4 though definitely makes sense because of FP64.
Right. I will relax the assertion check as suggested. > Either way patch is: > > Reviewed-by: Francisco Jerez <curroje...@riseup.net> > Thanks! Sam >> assert(inst->force_writemask_all || inst->group % inst->exec_size == >> 0); >> assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen)); >> assert(inst->mlen <= BRW_MAX_MSG_LENGTH); >> -- >> 2.7.4 >> >> _______________________________________________ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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