On Jul 1, 2016 1:04 AM, "Pohjolainen, Topi" <topi.pohjolai...@intel.com>
wrote:
>
> On Wed, Jun 29, 2016 at 05:37:35PM -0700, Jason Ekstrand wrote:
> > Eventually, this will be the actual view that gets passed into isl to
> > create the surface state. For now, we just use it for the format and
the
> > swizzle.
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp.c | 38
+++++++++++++++++++--------
> > src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++---------
> > src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 34
++++++++++++++++++++----
> > src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
> > src/mesa/drivers/dri/i965/gen8_blorp.c | 29 ++++----------------
> > 5 files changed, 64 insertions(+), 55 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 5e433d3..df92822 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -43,9 +43,11 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> > * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it
had better
> > * be a multiple of num_samples.
> > */
> > + unsigned layer_multiplier = 1;
> > if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> > mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
> > assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
> > + layer_multiplier = MAX2(mt->num_samples, 1);
> > }
> >
> > intel_miptree_check_level_layer(mt, level, layer);
> > @@ -61,13 +63,27 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> > info->aux_usage = ISL_AUX_USAGE_NONE;
> > }
> >
> > + info->view = (struct isl_view) {
> > + .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
> > + ISL_SURF_USAGE_TEXTURE_BIT,
> > + .format = ISL_FORMAT_UNSUPPORTED, /* Set later */
> > + .base_level = level,
> > + .levels = 1,
> > + .base_array_layer = layer / layer_multiplier,
> > + .array_len = 1,
> > + .channel_select = {
> > + ISL_CHANNEL_SELECT_RED,
> > + ISL_CHANNEL_SELECT_GREEN,
> > + ISL_CHANNEL_SELECT_BLUE,
> > + ISL_CHANNEL_SELECT_ALPHA,
> > + },
> > + };
> > +
> > info->level = level;
> > info->layer = layer;
> > info->width = minify(mt->physical_width0, level - mt->first_level);
> > info->height = minify(mt->physical_height0, level -
mt->first_level);
> >
> > - info->swizzle = SWIZZLE_XYZW;
> > -
> > if (format == MESA_FORMAT_NONE)
> > format = mt->format;
> >
> > @@ -75,8 +91,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> > case MESA_FORMAT_S_UINT8:
> > assert(info->surf.tiling == ISL_TILING_W);
> > /* Prior to Broadwell, we can't render to R8_UINT */
> > - info->brw_surfaceformat = brw->gen >= 8 ?
BRW_SURFACEFORMAT_R8_UINT :
> > -
BRW_SURFACEFORMAT_R8_UNORM;
> > + info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> > + BRW_SURFACEFORMAT_R8_UNORM;
>
> isl_view::format is of the type "enum isl_format" but we assigned it with
> BRW_SURFACEFORMAT?
ISL uses the hardware values so the two are interchangeable. I haven't yet
gone through the dri driver and deleted the BRW_SURFACEFORMAT defines. I
could, however fix this particular case while I'm in the neighborhood.
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