Looks good to me:
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>
Note: I think that patches 3-4 should be reviewed by a more seasoned
developer (specially patch 3).
On 01/07/16 07:07, Francisco Jerez wrote:
> There were two places in the driver doing a pipe control VF cache
> flush, one of them was missing this workaround, move it down into
> brw_emit_pipe_control_flush to make sure we don't miss it again.
> ---
> src/mesa/drivers/dri/i965/brw_pipe_control.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 586355d..14a8f7c 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -100,6 +100,16 @@ brw_emit_pipe_control_flush(struct brw_context *brw,
> uint32_t flags)
> if (brw->gen == 8)
> gen8_add_cs_stall_workaround_bits(&flags);
>
> + if (brw->gen == 9 &&
> + (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
> + /* Hardware workaround: SKL
> + *
> + * Emit Pipe Control with all bits set to zero before emitting
> + * a Pipe Control with VF Cache Invalidate set.
> + */
> + brw_emit_pipe_control_flush(brw, 0);
> + }
> +
> BEGIN_BATCH(6);
> OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
> OUT_BATCH(flags);
> @@ -322,15 +332,6 @@ brw_emit_mi_flush(struct brw_context *brw)
> } else {
> int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
> if (brw->gen >= 6) {
> - if (brw->gen == 9) {
> - /* Hardware workaround: SKL
> - *
> - * Emit Pipe Control with all bits set to zero before emitting
> - * a Pipe Control with VF Cache Invalidate set.
> - */
> - brw_emit_pipe_control_flush(brw, 0);
> - }
> -
> flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> PIPE_CONTROL_VF_CACHE_INVALIDATE |
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
