This patch series adds support for a (useful) subset of
GL_ARB_gpu_shader5 to every GPU in Mesa that supports GLSL 1.30 or
later. Many of these functions are needed to implement a lowering pass
for 64-bit integers on non-GL4 GPUs. It didn't make a lot of sense to
me to have an extension (public or private) that implemented everything
except bitfield{Extract,Insert,Reverse} and bitCount.
I have done almost no work in Gallium. I suspect that a number of cap
bits will need to be added to select specific lowering passes. For now,
every GPU that does not support GL_ARB_gpu_shader5 will lower
everything. I suspect that just about every GPU will be able to avoid
the ir_binop_imul_high lowering. It may be possible to avoid some of
the others on some GPUs... the software rasterizers should also be able
to avoid nearly all of them.
Patch 23 will never be pushed. I used this to test all of the lowering
passes on Intel GPUs using piglit, GLES CTS, and dEQP. I feel pretty
confident that the lowering passes will work as advertised on, say, nv50
or r500, but it would be nice for someone to actually test it. :)
Patch 24 needs some help. I want to optimize open-coded BFM, but I'm
not sure how to detect when that is valid.
The code is available in
https://cgit.freedesktop.org/~idr/mesa/log/?h=MESA_shader_integer_functions
and the tests are available in
https://cgit.freedesktop.org/~idr/piglit/log/?h=MESA_shader_integer_functions
docs/specs/MESA_shader_integer_functions.txt | 519 ++++++++++++++++
src/compiler/glsl/ast_to_hir.cpp | 3 +-
src/compiler/glsl/builtin_functions.cpp | 31 +-
src/compiler/glsl/glcpp/glcpp-parse.y | 3 +
src/compiler/glsl/glsl_parser_extras.cpp | 1 +
src/compiler/glsl/glsl_parser_extras.h | 2 +
src/compiler/glsl/ir_function.cpp | 12 +-
src/compiler/glsl/ir_optimization.h | 7 +
src/compiler/glsl/lower_instructions.cpp | 638 ++++++++++++++++++++
src/compiler/glsl/standalone_scaffolding.cpp | 2 +
src/compiler/glsl_types.cpp | 13 +-
src/compiler/nir/nir_opt_algebraic.py | 6 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +-
src/mesa/drivers/dri/i965/brw_fs.h | 4 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 96 ++-
src/mesa/drivers/dri/i965/brw_link.cpp | 25 +-
src/mesa/drivers/dri/i965/brw_vec4.h | 4 +
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 +
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 93 ++-
src/mesa/drivers/dri/i965/intel_extensions.c | 6 +-
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
src/mesa/state_tracker/st_extensions.c | 1 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 16 +-
25 files changed, 1440 insertions(+), 56 deletions(-)
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