From: Iago Toral Quiroga <ito...@igalia.com>
From the Cherryview PRM, Volume 7, 3D Media GPGPU Engine,
Register Region Restrictions:
"When source or destination is 64b (...), regioning in Align1
must follow these rules:
1. Source and destination horizontal stride must be aligned to
the same qword.
(...)"
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index b811953..c271e64 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -715,10 +715,37 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
case nir_op_u2f:
if (optimize_extract_to_float(instr, result))
return;
+ inst = bld.MOV(result, op[0]);
+ inst->saturate = instr->dest.saturate;
+ break;
case nir_op_f2d:
case nir_op_i2d:
case nir_op_u2d:
+ /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
+ *
+ * "When source or destination is 64b (...), regioning in Align1
+ * must follow these rules:
+ *
+ * 1. Source and destination horizontal stride must be aligned to
+ * the same qword.
+ * (...)"
+ *
+ * This means that 32-bit to 64-bit conversions need to have the 32-bit
+ * data elements aligned to 64-bit. This restriction does not apply to
+ * BDW and later.
+ */
+ if (devinfo->is_cherryview) {
+ fs_reg tmp = bld.vgrf(result.type, 1);
+ tmp = subscript(tmp, op[0].type, 0);
+ inst = bld.MOV(tmp, op[0]);
+ inst->regs_written =
+ inst->dst.component_size(bld.dispatch_width()) / REG_SIZE;
+ inst = bld.MOV(result, tmp);
+ inst->saturate = instr->dest.saturate;
+ break;
+ }
+ /* fallthrough */
case nir_op_d2f:
case nir_op_d2i:
case nir_op_d2u:
--
2.8.1
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