There's no real reason why we shouldn't set this bit. It does affect how
the sampler operates a bit but since you can have a 2D non-array view of a
2D_ARRAY texture that distinction is very weak. Also, this is what ISL
will do and we would like this change to be isolated from using ISL.
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 60589bc..2a7ae31 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -295,7 +295,7 @@ gen7_emit_texture_surface_state(struct brw_context *brw,
if (mt->halign == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
+ if (mt->target != GL_TEXTURE_3D)
surf[0] |= GEN7_SURFACE_IS_ARRAY;
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index abd6016..f4375ea 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -297,7 +297,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
format == BRW_SURFACEFORMAT_BC7_UNORM))
surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
- if (_mesa_is_array_texture(mt->target) || mt->target == GL_TEXTURE_CUBE_MAP)
+ if (mt->target != GL_TEXTURE_3D)
surf[0] |= GEN8_SURFACE_IS_ARRAY;
surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
--
2.5.0.400.gff86faf
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