Jason Ekstrand <ja...@jlekstrand.net> writes: > I was a little concerned when I first looked at this as to how simple it > was but I think lower_logical_send should handle it ok. > Heh, yeah, I was surprised too that it's actually less code to have SAMPLEINFO take the normal texturing path through logical send lowering rather than doing things manually. ;)
> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
>
Thanks!
> On May 20, 2016 10:49 PM, "Francisco Jerez" <curroje...@riseup.net> wrote:
>>
>> Seems like this texturing opcode was missing its logical counterpart
>> which would prevent it from taking advantage of the SIMD lowering
>> infrastructure, define it and plumb it through the back-end. At some
>> point we'll likely want to emit a single SAMPLEINFO message shared
>> among all channels irrespective of this change, but for the moment
>> this should be enough to get the intrinsic working in SIMD32 mode.
>> ---
>> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
>> src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +++++++++
>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 20 +++-----------------
>> src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
>> 4 files changed, 15 insertions(+), 17 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
>> index 458d690..b3075a6 100644
>> --- a/src/mesa/drivers/dri/i965/brw_defines.h
>> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
>> @@ -998,6 +998,7 @@ enum opcode {
>> SHADER_OPCODE_TG4_OFFSET,
>> SHADER_OPCODE_TG4_OFFSET_LOGICAL,
>> SHADER_OPCODE_SAMPLEINFO,
>> + SHADER_OPCODE_SAMPLEINFO_LOGICAL,
>>
>> /**
>> * Combines multiple sources of size 1 into a larger virtual GRF.
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> index c176807..0049334 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -742,6 +742,7 @@ fs_inst::components_read(unsigned i) const
>> case SHADER_OPCODE_LOD_LOGICAL:
>> case SHADER_OPCODE_TG4_LOGICAL:
>> case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
>> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
>> assert(src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM &&
>> src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
>> /* Texture coordinates. */
>> @@ -4113,6 +4114,7 @@ lower_sampler_logical_send_gen7(const fs_builder
> &bld, fs_inst *inst, opcode op,
>>
>> if (op == SHADER_OPCODE_TG4 || op == SHADER_OPCODE_TG4_OFFSET ||
>> offset_value.file != BAD_FILE ||
>> + op == SHADER_OPCODE_SAMPLEINFO ||
>> is_high_sampler(devinfo, sampler)) {
>> /* For general texture offsets (no txf workaround), we need a
> header to
>> * put them in. Note that we're only reserving space for it in the
>> @@ -4541,6 +4543,10 @@ fs_visitor::lower_logical_sends()
>> lower_sampler_logical_send(ibld, inst,
> SHADER_OPCODE_TG4_OFFSET);
>> break;
>>
>> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
>> + lower_sampler_logical_send(ibld, inst,
> SHADER_OPCODE_SAMPLEINFO);
>> + break;
>> +
>> case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
>> lower_surface_logical_send(ibld, inst,
>> SHADER_OPCODE_UNTYPED_SURFACE_READ,
>> @@ -4720,6 +4726,9 @@ get_lowered_simd_width(const struct brw_device_info
> *devinfo,
>> return (inst->src[FB_WRITE_LOGICAL_SRC_COLOR1].file != BAD_FILE ?
>> 8 : inst->exec_size);
>>
>> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
>> + return MIN2(16, inst->exec_size);
>> +
>> case SHADER_OPCODE_TXD_LOGICAL:
>> /* TXD is unsupported in SIMD16 mode. */
>> return 8;
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
>> index 530184a..c236eb2 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
>> @@ -4168,23 +4168,9 @@ fs_visitor::nir_emit_texture(const fs_builder
> &bld, nir_tex_instr *instr)
>> else
>> opcode = SHADER_OPCODE_TG4_LOGICAL;
>> break;
>> - case nir_texop_texture_samples: {
>> - fs_reg dst = retype(get_nir_dest(instr->dest),
> BRW_REGISTER_TYPE_D);
>> -
>> - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, 4);
>> - fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, tmp,
>> - bld.vgrf(BRW_REGISTER_TYPE_D, 1),
>> - srcs[TEX_LOGICAL_SRC_SURFACE],
>> - srcs[TEX_LOGICAL_SRC_SURFACE]);
>> - inst->mlen = 1;
>> - inst->header_size = 1;
>> - inst->base_mrf = -1;
>> - inst->regs_written = 4 * (dispatch_width / 8);
>> -
>> - /* Pick off the one component we care about */
>> - bld.MOV(dst, tmp);
>> - return;
>> - }
>> + case nir_texop_texture_samples:
>> + opcode = SHADER_OPCODE_SAMPLEINFO_LOGICAL;
>> + break;
>> case nir_texop_samples_identical: {
>> fs_reg dst = retype(get_nir_dest(instr->dest),
> BRW_REGISTER_TYPE_D);
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
>> index 18242ba..b615528 100644
>> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
>> @@ -260,6 +260,8 @@ brw_instruction_name(const struct brw_device_info
> *devinfo, enum opcode op)
>> return "tg4_offset_logical";
>> case SHADER_OPCODE_SAMPLEINFO:
>> return "sampleinfo";
>> + case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
>> + return "sampleinfo_logical";
>>
>> case SHADER_OPCODE_SHADER_TIME_ADD:
>> return "shader_time_add";
>> --
>> 2.7.3
>>
>> _______________________________________________
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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