The precise trig workaround is in NIR now, removing
the performance penalty that was the rationale behind
the option.
---
src/mesa/drivers/dri/i965/brw_compiler.c | 2 --
src/mesa/drivers/dri/i965/brw_compiler.h | 6 ------
src/mesa/drivers/dri/i965/brw_nir.c | 3 +--
3 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 82131db..0a28c25 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -145,8 +145,6 @@ brw_compiler_create(void *mem_ctx, const struct
brw_device_info *devinfo)
brw_fs_alloc_reg_sets(compiler);
brw_vec4_alloc_reg_set(compiler);
- compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
-
compiler->scalar_stage[MESA_SHADER_VERTEX] =
devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index 0db1d0d..52af037 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -92,12 +92,6 @@ struct brw_compiler {
bool scalar_stage[MESA_SHADER_STAGES];
struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
-
- /**
- * Apply workarounds for SIN and COS output range problems.
- * This can negatively impact performance.
- */
- bool precise_trig;
};
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 9afd036..5ba4e12 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -442,8 +442,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler,
nir_shader *nir)
if (nir->stage == MESA_SHADER_GEOMETRY)
OPT(nir_lower_gs_intrinsics);
- if (compiler->precise_trig)
- OPT(brw_nir_apply_trig_workarounds);
+ OPT(brw_nir_apply_trig_workarounds);
static const nir_lower_tex_options tex_options = {
.lower_txp = ~0,
--
2.1.2
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