On Wed, May 11, 2016 at 4:22 PM, Jordan Justen <jordan.l.jus...@intel.com> wrote:
> git://people.freedesktop.org/~jljusten/mesa anv-l3-v1 > > This series is related to this bug: > > https://bugs.freedesktop.org/show_bug.cgi?id=94468 > > Since we have a work-around for that bug currently, this doesn't fix > it. It does allow us to remove the work-around though. > > Running through jenkins, I see 1 consistent regression only on Haswell > for an image load/store test that uses compute shaders. Even with the > regression, I think it is better to merge this series. > > Jordan Justen (5): > genxml/hsw: Add L3 cache control registers > anv: Keep track of whether the data cache should be enabled in L3 > anv/gen7: Add memory barrier to vkCmdWaitEvents call > anv: Port L3 cache programming from i965 > Revert "HACK: Don't re-configure L3$ in render stages pre-BDW" > 1-3 and 5 are Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> 4 is Acked-by: Jason Ekstrand <ja...@jlekstrand.net> > > src/intel/genxml/gen75.xml | 8 + > src/intel/vulkan/Makefile.sources | 4 + > src/intel/vulkan/anv_genX.h | 4 +- > src/intel/vulkan/anv_pipeline.c | 41 ++- > src/intel/vulkan/anv_private.h | 13 +- > src/intel/vulkan/gen7_cmd_buffer.c | 100 +------ > src/intel/vulkan/gen8_cmd_buffer.c | 74 +---- > src/intel/vulkan/genX_cmd_buffer.c | 13 +- > src/intel/vulkan/genX_l3.c | 541 > +++++++++++++++++++++++++++++++++++++ > src/intel/vulkan/genX_pipeline.c | 4 + > 10 files changed, 617 insertions(+), 185 deletions(-) > create mode 100644 src/intel/vulkan/genX_l3.c > > -- > 2.8.1 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev >
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