The buffer is quite large, but should only be allocated if the
application uses tessellation. Most non-games don't.
Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.h | 1 +
src/gallium/drivers/radeonsi/si_state_shaders.c | 17 +++++++++++++++++
4 files changed, 20 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 61d5578..10123d4 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -48,6 +48,7 @@ static void si_destroy_context(struct pipe_context *context)
pipe_resource_reference(&sctx->esgs_ring, NULL);
pipe_resource_reference(&sctx->gsvs_ring, NULL);
pipe_resource_reference(&sctx->tf_ring, NULL);
+ pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
r600_resource_reference(&sctx->border_color_buffer, NULL);
free(sctx->border_color_table);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index d31e9a9..b219dd4 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -256,6 +256,7 @@ struct si_context {
struct pipe_resource *esgs_ring;
struct pipe_resource *gsvs_ring;
struct pipe_resource *tf_ring;
+ struct pipe_resource *tess_offchip_ring;
union pipe_color_union *border_color_table; /* in CPU memory,
any endian */
struct r600_resource *border_color_buffer;
union pipe_color_union *border_color_map; /* in VRAM (slow
access), little endian */
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index f2a3b03..6d4346b 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -155,6 +155,7 @@ struct si_shader_data {
/* Private read-write buffer slots. */
enum {
SI_HS_RING_TESS_FACTOR,
+ SI_HS_RING_TESS_OFFCHIP,
SI_ES_RING_ESGS,
SI_GS_RING_ESGS,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 0bfd7e8..0fa32c8 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1772,6 +1772,15 @@ static void si_init_tess_factor_ring(struct si_context
*sctx)
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
+ /* The size is derived from 256 blocks of 8192 dwords each, as set in
+ * R_03093C_VGT_HS_OFFCHIP_PARAM. */
+ sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen,
+ PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT,
+ 8 * 1024 * 1024);
+ if (!sctx->tess_offchip_ring)
+ return;
+
si_init_config_add_vgt_flush(sctx);
/* Append these registers to the init config state. */
@@ -1787,6 +1796,10 @@ static void si_init_tess_factor_ring(struct si_context
*sctx)
r600_resource(sctx->tf_ring)->gpu_address >> 8);
}
+ si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
+ S_03093C_OFFCHIP_BUFFERING(0xFF) |
+ S_03093C_OFFCHIP_GRANULARITY(V_03093C_X_8K_DWORDS));
+
/* Flush the context to re-emit the init_config state.
* This is done only once in a lifetime of a context.
*/
@@ -1796,6 +1809,10 @@ static void si_init_tess_factor_ring(struct si_context
*sctx)
si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
0, sctx->tf_ring->width0, false, false, 0, 0, 0);
+
+ si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
+ sctx->tess_offchip_ring, 0,
+ sctx->tess_offchip_ring->width0, false, false, 0, 0,
0);
}
/**
--
2.8.2
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