From: Connor Abbott <connor.w.abb...@intel.com>
The destination has to have the same source as the type, or else the
simulator will complain. As a result, we need to emit a CMP that
outputs a 64-bit wide result and then do a strided MOV to pick out the
low 32 bits of each channel.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 34 +++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 0ce25a0..70ffc6d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -891,23 +891,51 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
}
case nir_op_flt:
+ case nir_op_fge:
+ case nir_op_feq:
+ case nir_op_fne: {
+ fs_reg dest = result;
+ if (nir_src_bit_size(instr->src[0].src) > 32) {
+ dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
+ }
+ brw_conditional_mod cond;
+ switch (instr->op) {
+ case nir_op_flt:
+ cond = BRW_CONDITIONAL_L;
+ break;
+ case nir_op_fge:
+ cond = BRW_CONDITIONAL_GE;
+ break;
+ case nir_op_feq:
+ cond = BRW_CONDITIONAL_Z;
+ break;
+ case nir_op_fne:
+ cond = BRW_CONDITIONAL_NZ;
+ break;
+ default:
+ unreachable("bad opcode");
+ }
+ bld.CMP(dest, op[0], op[1], cond);
+ if (nir_src_bit_size(instr->src[0].src) > 32) {
+ bld.MOV(result, stride(retype(dest, BRW_REGISTER_TYPE_UD), 2));
+ }
+ break;
+ }
+
case nir_op_ilt:
case nir_op_ult:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
break;
- case nir_op_fge:
case nir_op_ige:
case nir_op_uge:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_GE);
break;
- case nir_op_feq:
case nir_op_ieq:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_Z);
break;
- case nir_op_fne:
case nir_op_ine:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_NZ);
break;
--
2.5.0
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