---
src/mesa/drivers/dri/i965/brw_context.h | 4 +--
src/mesa/drivers/dri/i965/gen6_queryobj.c | 43 ---------------------------
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 37 +++++++++++++++++++++++
3 files changed, 39 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 28c5989..e4a8507 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1430,8 +1430,6 @@ void brw_emit_query_end(struct brw_context *brw);
void gen6_init_queryobj_functions(struct dd_function_table *functions);
void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
-void brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
/** brw_conditional_render.c */
void brw_init_conditional_render_functions(struct dd_function_table
*functions);
@@ -1448,6 +1446,8 @@ void brw_load_register_mem64(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
+void brw_store_register_mem64(struct brw_context *brw,
+ drm_intel_bo *bo, uint32_t reg, uint32_t offset);
/*======================================================================
* brw_state_dump.c
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index e788de5..960ccfd 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -39,49 +39,6 @@
#include "intel_batchbuffer.h"
#include "intel_reg.h"
-/*
- * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
- *
- * Only TIMESTAMP and PS_DEPTH_COUNT have special PIPE_CONTROL support; other
- * counters have to be read via the generic MI_STORE_REGISTER_MEM.
- *
- * Callers must explicitly flush the pipeline to ensure the desired value is
- * available.
- */
-void
-brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
-{
- assert(brw->gen >= 6);
-
- /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
- * read a full 64-bit register, we need to do two of them.
- */
- if (brw->gen >= 8) {
- BEGIN_BATCH(8);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(6);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
- ADVANCE_BATCH();
- }
-}
-
static void
write_primitives_generated(struct brw_context *brw,
drm_intel_bo *query_bo, int stream, int idx)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index e41f927..cd5d301 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -537,3 +537,40 @@ brw_load_register_mem64(struct brw_context *brw,
{
load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
2);
}
+
+/*
+ * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
+ */
+void
+brw_store_register_mem64(struct brw_context *brw,
+ drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+{
+ assert(brw->gen >= 6);
+
+ /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
+ * read a full 64-bit register, we need to do two of them.
+ */
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(8);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg + sizeof(uint32_t));
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset + sizeof(uint32_t));
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(6);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg + sizeof(uint32_t));
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset + sizeof(uint32_t));
+ ADVANCE_BATCH();
+ }
+}
--
2.8.0.rc3
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