I added some CS_PARTIAL_FLUSH events after MArek's response. I haven't been able to detect anything wrong without them. However at least theoretically some event has to wait on CS shaders at the new points.(e.g fbo change clearly has a potential write after read hazard otherwise).
I also updated the update cap patch, as I discovered that writing the USER_DATA registers from a COPY_DATA packet was disallowed by the kernel with the SI CS checker. Now that that has been fixed in the kernel, the new patch checks for the drm version that has the fix. Bas Nieuwenhuizen (2): radeonsi: do not do two full flushes on every compute dispatch radeonsi: enable TGSI support cap for compute shaders docs/GL3.txt | 4 ++-- docs/relnotes/11.3.0.html | 1 + src/gallium/drivers/radeon/r600_pipe_common.c | 21 ++++++++++++++++----- src/gallium/drivers/radeonsi/si_compute.c | 17 ++--------------- src/gallium/drivers/radeonsi/si_cp_dma.c | 6 ++++-- src/gallium/drivers/radeonsi/si_descriptors.c | 3 ++- src/gallium/drivers/radeonsi/si_hw_context.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 15 +++++++++++++-- src/gallium/drivers/radeonsi/si_state.c | 12 ++++++++---- 9 files changed, 49 insertions(+), 31 deletions(-) -- 2.8.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
