On Sun, Apr 17, 2016 at 1:43 AM, Bas Nieuwenhuizen
<b...@basnieuwenhuizen.nl> wrote:
> v2: Use 32 byte alignment.
>
> Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
> ---
> src/gallium/drivers/radeonsi/si_descriptors.c | 30
> +++++++++++++++++++--------
> src/gallium/drivers/radeonsi/si_state.h | 3 +++
> 2 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 7fc1461..a937973 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -98,7 +98,8 @@ static void si_init_descriptors(struct si_descriptors *desc,
> unsigned shader_userdata_index,
> unsigned element_dw_size,
> unsigned num_elements,
> - const uint32_t *null_descriptor)
> + const uint32_t *null_descriptor,
> + unsigned *ce_offset)
> {
> int i;
>
> @@ -109,6 +110,10 @@ static void si_init_descriptors(struct si_descriptors
> *desc,
> desc->num_elements = num_elements;
> desc->list_dirty = true; /* upload the list before the next draw */
> desc->shader_userdata_offset = shader_userdata_index * 4;
> + desc->ce_offset = *ce_offset;
> +
> + /* make sure that ce_offset stays 32 byte aligned */
> + *ce_offset += align(element_dw_size * num_elements * 4, 32);
Please define SI_GLOBAL_L2_CACHE_LINE_SIZE 64 in si_pipe.h and use that.
Aligning the offset is indeed a good idea, but aligning to the cache
line size should be even better.
Marek
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