2011/8/29 <deathsim...@vodafone.de>:
> From: Christian König <deathsim...@vodafone.de>
>
> The layersize calculation is slightly different on +evergreen.
> This makes mpeg2 video decoding and piglits texture-packed-formats
> test work correctly on this hardware.
Does this patch work as well? I think it's somewhat cleaner and
covers other cases that may be affected as well. In theory we should
switch all the code to use linear aligned rather than linear general
for linear formats.
Alex
> ---
> src/gallium/drivers/r600/r600_texture.c | 6 +++++-
> 1 files changed, 5 insertions(+), 1 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_texture.c
> b/src/gallium/drivers/r600/r600_texture.c
> index 7c1bd9d..e5783b9 100644
> --- a/src/gallium/drivers/r600/r600_texture.c
> +++ b/src/gallium/drivers/r600/r600_texture.c
> @@ -262,7 +262,11 @@ static void r600_setup_miptree(struct pipe_screen
> *screen,
> nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
> nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
>
> - layer_size = nblocksx * nblocksy * blocksize;
> + if (chipc >= EVERGREEN && array_mode ==
> V_038000_ARRAY_LINEAR_GENERAL)
> + layer_size = align(nblocksx, 64) * nblocksy *
> blocksize;
> + else
> + layer_size = nblocksx * nblocksy * blocksize;
> +
> if (ptex->target == PIPE_TEXTURE_CUBE) {
> if (chipc >= R700)
> size = layer_size * 8;
> --
> 1.7.4.1
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
From 46432adf5ed9d98ed1ae7bf6f1ec054320f09e2d Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deuc...@amd.com>
Date: Tue, 30 Aug 2011 12:45:18 -0400
Subject: [PATCH] r600g: use linear aligned alignment requirements for evergreen
The texture hardware technically doesn't support linear general,
only linear aligned (only the CB supports linear general). As
such it requires linear aligned alignment. In theory this applies
to all asics, but in practice it only seems to affect evergreen+.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
src/gallium/drivers/r600/r600_texture.c | 11 ++++++++++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index e41fe11..b4a93d6 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -87,6 +87,8 @@ static unsigned r600_get_block_alignment(struct pipe_screen *screen,
unsigned array_mode)
{
struct r600_screen* rscreen = (struct r600_screen *)screen;
+ struct radeon *radeon = rscreen->radeon;
+ enum chip_class chipc = r600_get_family_class(radeon);
unsigned pixsize = util_format_get_blocksize(format);
int p_align;
@@ -105,7 +107,14 @@ static unsigned r600_get_block_alignment(struct pipe_screen *screen,
break;
case V_038000_ARRAY_LINEAR_GENERAL:
default:
- p_align = rscreen->tiling_info->group_bytes / pixsize;
+ /* The texture block doesn't support linear general, if you
+ * set it, it gets mapped to linear aligned (in theory on all
+ * chips, but in practice it seems to only affect evergreen).
+ */
+ if (chipc >= EVERGREEN)
+ p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
+ else
+ p_align = rscreen->tiling_info->group_bytes / pixsize;
break;
}
return p_align;
--
1.7.1.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
