---
src/mesa/drivers/dri/i965/brw_vec4.h | 20 +++++++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 73 ++++++++++++++++++++++++
2 files changed, 93 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 6e67aa0..7bd59ad 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -402,6 +402,26 @@ public:
vec4_instruction *emit(enum opcode opcode, dst_reg dst,
src_reg src0, src_reg src1, src_reg src2);
+ vec4_instruction *MOV(dst_reg dst, src_reg src0);
+ vec4_instruction *NOT(dst_reg dst, src_reg src0);
+ vec4_instruction *RNDD(dst_reg dst, src_reg src0);
+ vec4_instruction *RNDE(dst_reg dst, src_reg src0);
+ vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
+ vec4_instruction *FRC(dst_reg dst, src_reg src0);
+ vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
+ uint32_t condition);
+ vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
+ vec4_instruction *IF(uint32_t predicate);
+
bool try_rewrite_rhs_to_dst(ir_assignment *ir,
dst_reg dst,
src_reg src,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 7b0d179..68c0ed9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -120,6 +120,79 @@ vec4_visitor::emit(enum opcode opcode)
return emit(new(mem_ctx) vec4_instruction(this, opcode, dst_reg()));
}
+#define ALU1(op) \
+ vec4_instruction * \
+ vec4_visitor::op(dst_reg dst, src_reg src0) \
+ { \
+ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
+ src0); \
+ }
+
+#define ALU2(op) \
+ vec4_instruction * \
+ vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
+ { \
+ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
+ src0, src1); \
+ }
+
+ALU1(NOT)
+ALU1(MOV)
+ALU1(FRC)
+ALU1(RNDD)
+ALU1(RNDE)
+ALU1(RNDZ)
+ALU2(ADD)
+ALU2(MUL)
+ALU2(MACH)
+ALU2(AND)
+ALU2(OR)
+ALU2(XOR)
+ALU2(DP3)
+ALU2(DP4)
+
+/** Gen4 predicated IF. */
+vec4_instruction *
+vec4_visitor::IF(uint32_t predicate)
+{
+ vec4_instruction *inst;
+
+ inst = new(mem_ctx) vec4_instruction(this, BRW_OPCODE_IF);
+ inst->predicate = predicate;
+
+ return inst;
+}
+
+/** Gen6+ IF with embedded comparison. */
+vec4_instruction *
+vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
+{
+ assert(intel->gen >= 6);
+
+ vec4_instruction *inst;
+
+ inst = new(mem_ctx) vec4_instruction(this, BRW_OPCODE_IF);
+ inst->conditional_mod = condition;
+
+ return inst;
+
+}
+
+vec4_instruction *
+vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition)
+{
+ assert(intel->gen >= 6);
+
+ vec4_instruction *inst;
+
+ inst = new(mem_ctx)vec4_instruction(this, BRW_OPCODE_CMP, dst,
+ src0, src1, src_reg());
+ inst->conditional_mod = condition;
+
+ return inst;
+
+}
+
void
vec4_visitor::emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned
elements)
{
--
1.7.5.4
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