Matt Turner <matts...@gmail.com> writes: > Missing this causes an assertion failure in the scheduler with the next > patch. > --- > src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 - > src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 4 +++- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp > b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp > index 549b707..d12231e 100644 > --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp > +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp > @@ -1923,7 +1923,6 @@ generate_code(struct brw_codegen *p, > case TCS_OPCODE_SRC0_010_IS_ZERO:
The name of this opcode becomes rather misleading after you remove the
implicit condmod. Now it just moves a vec4 half into the null register,
it doesn't necessarily care whether it's zero or not. I don't have much
better opcode name proposals right now though, so,
Acked-by: Francisco Jerez <curroje...@riseup.net>
> /* If src_reg had stride like fs_reg, we wouldn't need this. */
> brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
> - brw_inst_set_cond_modifier(devinfo, brw_last_inst,
> BRW_CONDITIONAL_Z);
> break;
>
> case TCS_OPCODE_RELEASE_INPUT:
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> index 8f77b59..800e741 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
> @@ -184,7 +184,9 @@ vec4_tcs_visitor::emit_thread_end()
> * we don't have stride in the vec4 world, nor UV immediates in
> * align16, so we need an opcode to get invocation_id<0,4,0>.
> */
> - emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), invocation_id);
> + set_condmod(BRW_CONDITIONAL_Z,
> + emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
> + invocation_id));
> emit(IF(BRW_PREDICATE_NORMAL));
> for (unsigned i = 0; i < key->input_vertices; i += 2) {
> /* If we have an odd number of input vertices, the last will be
> --
> 2.4.10
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