I had a few comments, but by-and-large it looks fine. If you think you need to do a respin, that's fine. Otherwise, with the comments addressed,
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> On Mon, Mar 7, 2016 at 12:45 AM, Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > Hello, > > Iago and I are working on adding FP64 support to i965 drivers [0] with > the help of Connor and Jason (Thanks!). That support requires changes > in NIR to include the bit-size information in the data types and also > modifications in the opcodes to use sized types as needed. > > This means that all NIR clients should take that information into > consideration as well, since backends are now expected to see sized NIR > types and they need to handle them properly. > > This batch is the smallest set of NIR patches required to > incorporate sized types together with the minimum set of changes > required to i965, freedreno and vc4 that we have identified. Rob Clark > and Eric Anholt checked that freedreno and vc4 drivers respectively > work fine with these changes. > > We have verified that with these changes there are no regressions in > Piglit for i965, which does the minimum necessary to deal with sized > types at this point. We tested on gen5, gen6, gen7 and gen8. We don't > have gen4 hardware available, so trying this would also require > involvement from other people with access to this hardware. > > With this series, drivers should be able to work normally with both > sized and unsized types (mostly by ignoring the size aspect of the > type). > > The rest of the fp64 work that we hope to send soon for review will add > further changes to ensure that we get correct bit-sized types wherever > we need them, but we will postpone this until we actually need to care > about different bit-sizes, when we send the fp64 for review, since that > requires a lot more changes. > > The reason we are sending this part ahead is that the inclusion of sized > types in NIR together with the bit-size information affects all drivers > using NIR, and since it affects a lot of NIR opcodes (that now need to > be defined using the corresponding bit-sized types) it is much easier to > review and land this ahead of the rest of the series and have everyone > be aware of this change as soon as possible. > > Because of this it would also be great if new code checked in after this > series also tries to incorporate bit-size information to the types in > NIR and the drivers, even if the drivers can eat the unsized types too > for now. We will try to fix anything that slips in as we rebase our > fp64 branch though. > > We would like to land this batch of patches in NIR ahead of the rest > of the fp64 changes, which will use sized types extensively. This is > important because the change is significant and it is important that > new code landing in master is aware of this as soon as possible. > > Our idea is to squash these patches together into a single commit before > pushing them to master. We keep them separate here to facilitate the > review. > > Thanks, > > Sam > > [0] https://bugs.freedesktop.org/show_bug.cgi?id=92760 > > Connor Abbott (10): > nir/types: add a function to get the bitsize of a base type > nir: add double constant types > nir: update opcode definitions for different bit sizes > nir: handle different bit sizes when constant folding > i965: fix brw_type_for_nir_type() for sized types > i965: fix brw_glsl_base_type_for_nir_type() for sized types > nir: add nir_src_bit_size() helper > nir: add nir_dest_bit_size() helper > nir: add a bit_size parameter to nir_ssa_dest_init > nir: propagate bitsize information in nir_search > > Iago Toral Quiroga (1): > vc4: adapt to new sized alu types > > Jason Ekstrand (2): > nir: Add explicitly sized types > nir: Add a bit_size to nir_register and nir_ssa_def > > Samuel Iglesias Gonsálvez (1): > i965/nir: fix check to resolve booleans to work with sized > nir_alu_type > > src/compiler/nir/glsl_to_nir.cpp | 22 +- > src/compiler/nir/nir.c | 14 +- > src/compiler/nir/nir.h | 51 ++++- > src/compiler/nir/nir_algebraic.py | 22 +- > src/compiler/nir/nir_builder.h | 33 ++- > src/compiler/nir/nir_clone.c | 3 +- > src/compiler/nir/nir_constant_expressions.h | 2 +- > src/compiler/nir/nir_constant_expressions.py | 246 > ++++++++++++-------- > src/compiler/nir/nir_from_ssa.c | 6 +- > src/compiler/nir/nir_lower_alu_to_scalar.c | 10 +- > src/compiler/nir/nir_lower_atomics.c | 6 +- > src/compiler/nir/nir_lower_clip.c | 2 +- > src/compiler/nir/nir_lower_io.c | 3 +- > src/compiler/nir/nir_lower_locals_to_regs.c | 7 +- > src/compiler/nir/nir_lower_phis_to_scalar.c | 10 +- > src/compiler/nir/nir_lower_tex.c | 2 +- > src/compiler/nir/nir_lower_two_sided_color.c | 2 +- > src/compiler/nir/nir_lower_var_copies.c | 5 +- > src/compiler/nir/nir_lower_vars_to_ssa.c | 12 +- > src/compiler/nir/nir_opcodes.py | 144 ++++++------ > src/compiler/nir/nir_opt_constant_folding.c | 24 +- > src/compiler/nir/nir_opt_peephole_select.c | 3 +- > src/compiler/nir/nir_search.c | 247 > +++++++++++++++++++-- > src/compiler/nir/nir_search.h | 8 +- > src/compiler/nir/nir_to_ssa.c | 6 +- > src/compiler/nir/nir_validate.c | 42 +++- > src/compiler/nir_types.h | 21 ++ > src/gallium/auxiliary/nir/tgsi_to_nir.c | 14 +- > .../drivers/freedreno/ir3/ir3_nir_lower_if_else.c | 2 +- > src/gallium/drivers/vc4/vc4_nir_lower_blend.c | 4 +- > src/gallium/drivers/vc4/vc4_nir_lower_io.c | 6 +- > src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c | 2 +- > src/gallium/drivers/vc4/vc4_program.c | 7 +- > src/mesa/drivers/dri/i965/brw_nir.c | 18 ++ > .../dri/i965/brw_nir_analyze_boolean_resolves.c | 2 +- > .../drivers/dri/i965/brw_nir_opt_peephole_ffma.c | 7 +- > src/mesa/program/prog_to_nir.c | 10 +- > 37 files changed, 760 insertions(+), 265 deletions(-) > > -- > 2.7.0 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev >
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