Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_nir.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index d405991..3cb6123 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -641,6 +641,17 @@ brw_create_nir(struct brw_context *brw,
/* First, lower the GLSL IR or Mesa IR to NIR */
if (shader_prog) {
nir = glsl_to_nir(shader_prog, stage, options);
+
+ if (nir->stage == MESA_SHADER_TESS_EVAL &&
+ shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
+ const struct gl_program *tcs =
+ shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]->Program;
+ /* Work around the TCS having bonus outputs used as shared memory
+ * segments, which makes OutputsWritten not match InputsRead
+ */
+ nir->info.inputs_read = tcs->OutputsWritten;
+ nir->info.patch_inputs_read = tcs->PatchOutputsWritten;
+ }
} else {
nir = prog_to_nir(prog, options);
OPT_V(nir_convert_to_ssa); /* turn registers into SSA */
--
2.6.3
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