[Mesa-dev] [PATCH 7/7] i965/vec4: Make uniform offsets be in terms of bytes

[Jason Ekstrand]

This makes all uniform offsets be in terms of bytes starting from
nir_lower_uniforms.  We convert to vec4's before we encode it in the
UNIFORM register file, but reladdr is in terms of bytes all the way down to
where we lower it to a pull constant load.
---
 src/mesa/drivers/dri/i965/brw_nir.c            | 9 ++++++++-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp     | 8 ++++++--
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 +--
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index a33fb31..de9581f 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -177,6 +177,12 @@ type_size_scalar_bytes(const struct glsl_type *type)
    return type_size_scalar(type) * 4;
 }
 
+static int
+type_size_vec4_bytes(const struct glsl_type *type)
+{
+   return type_size_vec4(type) * 16;
+}
+
 static void
 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 {
@@ -186,7 +192,8 @@ brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
       nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes);
    } else {
       nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
-                               type_size_vec4);
+                               type_size_vec4_bytes);
+      nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 16d3a06..657c5f8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -704,10 +704,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
*instr)
       has_indirect = true;
       /* fallthrough */
    case nir_intrinsic_load_uniform: {
+      /* Offsets are in bytes but they should always be multiples of 16 */
+      assert(instr->const_index[0] % 4 == 0);
+      assert(instr->const_index[1] % 4 == 0);
+
       dest = get_nir_dest(instr->dest);
 
-      src = src_reg(dst_reg(UNIFORM, instr->const_index[0]));
-      src.reg_offset = instr->const_index[1];
+      src = src_reg(dst_reg(UNIFORM, instr->const_index[0] / 16));
+      src.reg_offset = instr->const_index[1] / 16;
 
       if (has_indirect) {
          src_reg tmp = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_D, 1);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 51e6227..64f87dc 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1472,8 +1472,7 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, 
vec4_instruction *inst,
       src_reg index = src_reg(this, glsl_type::int_type);
 
       emit_before(block, inst, ADD(dst_reg(index), *reladdr,
-                                   brw_imm_d(reg_offset)));
-      emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
+                                   brw_imm_d(reg_offset * 16)));
 
       return index;
    } else if (devinfo->gen >= 8) {
-- 
2.5.0.400.gff86faf

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