Hi,
Mesa i965 instruction scheduler latency values look weird.
For example:
----------------------
void
schedule_node::set_latency_gen7(bool is_haswell)
{
switch (inst->opcode) {
...
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
/* Test code:
...
* Running it 100 times as fragment shader on a 128x128 quad
* gives an average latency of 583 cycles per surface read,
* standard deviation 0.9%.
*/
latency = is_haswell ? 300 : 600;
break;
...
schedule_node::schedule_node(backend_instruction *inst,
instruction_scheduler *sched)
{
...
if (!sched->post_reg_alloc)
this->latency = 1;
else if (devinfo->gen >= 6)
set_latency_gen7(devinfo->is_haswell);
else
set_latency_gen4();
}
----------------------
(I.e. for data reads use 300 on HSW, and 600 on everything else GEN6+...)
Are the tests referred in comments still available somewhere?
I'd like to run them to check from performance counters whether they're
limited by what the tests expect.
- Eero
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