This is actually just the message descriptor for Gen6+ dataport access;
it has nothing to do with the render cache. Access to the sampler cache
and constant cache also would use this struct; rename for clarity.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_disasm.c | 24 ++++++++++----------
src/mesa/drivers/dri/i965/brw_eu_emit.c | 36 +++++++++++++++---------------
src/mesa/drivers/dri/i965/brw_structs.h | 2 +-
3 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 111cb99..af41c84 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -967,12 +967,12 @@ int brw_disasm (FILE *file, struct brw_instruction *inst,
int gen)
case BRW_MESSAGE_TARGET_DATAPORT_READ:
if (gen >= 6) {
format (file, " (%d, %d, %d, %d, %d, %d)",
- inst->bits3.dp_render_cache.binding_table_index,
- inst->bits3.dp_render_cache.msg_control,
- inst->bits3.dp_render_cache.msg_type,
- inst->bits3.dp_render_cache.send_commit_msg,
- inst->bits3.dp_render_cache.msg_length,
- inst->bits3.dp_render_cache.response_length);
+ inst->bits3.gen6_dp.binding_table_index,
+ inst->bits3.gen6_dp.msg_control,
+ inst->bits3.gen6_dp.msg_type,
+ inst->bits3.gen6_dp.send_commit_msg,
+ inst->bits3.gen6_dp.msg_length,
+ inst->bits3.gen6_dp.response_length);
} else if (gen >= 5 /* FINISHME: || is_g4x */) {
format (file, " (%d, %d, %d)",
inst->bits3.dp_read_gen5.binding_table_index,
@@ -988,12 +988,12 @@ int brw_disasm (FILE *file, struct brw_instruction *inst,
int gen)
case BRW_MESSAGE_TARGET_DATAPORT_WRITE:
if (gen >= 6) {
format (file, " (%d, %d, %d, %d, %d, %d)",
- inst->bits3.dp_render_cache.binding_table_index,
- inst->bits3.dp_render_cache.msg_control,
- inst->bits3.dp_render_cache.msg_type,
- inst->bits3.dp_render_cache.send_commit_msg,
- inst->bits3.dp_render_cache.msg_length,
- inst->bits3.dp_render_cache.response_length);
+ inst->bits3.gen6_dp.binding_table_index,
+ inst->bits3.gen6_dp.msg_control,
+ inst->bits3.gen6_dp.msg_type,
+ inst->bits3.gen6_dp.send_commit_msg,
+ inst->bits3.gen6_dp.msg_length,
+ inst->bits3.gen6_dp.response_length);
} else {
format (file, " (%d, %d, %d, %d)",
inst->bits3.dp_write.binding_table_index,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 82b7137..31a8f2e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -487,15 +487,15 @@ static void brw_set_dp_write_message( struct brw_context
*brw,
brw_set_src1(insn, brw_imm_ud(0));
if (intel->gen >= 6) {
- insn->bits3.dp_render_cache.binding_table_index = binding_table_index;
- insn->bits3.dp_render_cache.msg_control = msg_control;
- insn->bits3.dp_render_cache.pixel_scoreboard_clear =
pixel_scoreboard_clear;
- insn->bits3.dp_render_cache.msg_type = msg_type;
- insn->bits3.dp_render_cache.send_commit_msg = send_commit_msg;
- insn->bits3.dp_render_cache.header_present = header_present;
- insn->bits3.dp_render_cache.response_length = response_length;
- insn->bits3.dp_render_cache.msg_length = msg_length;
- insn->bits3.dp_render_cache.end_of_thread = end_of_thread;
+ insn->bits3.gen6_dp.binding_table_index = binding_table_index;
+ insn->bits3.gen6_dp.msg_control = msg_control;
+ insn->bits3.gen6_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
+ insn->bits3.gen6_dp.msg_type = msg_type;
+ insn->bits3.gen6_dp.send_commit_msg = send_commit_msg;
+ insn->bits3.gen6_dp.header_present = header_present;
+ insn->bits3.gen6_dp.response_length = response_length;
+ insn->bits3.gen6_dp.msg_length = msg_length;
+ insn->bits3.gen6_dp.end_of_thread = end_of_thread;
/* We always use the render cache for write messages */
insn->header.destreg__conditionalmod =
GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
@@ -545,15 +545,15 @@ brw_set_dp_read_message(struct brw_context *brw,
else
target_function = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
- insn->bits3.dp_render_cache.binding_table_index = binding_table_index;
- insn->bits3.dp_render_cache.msg_control = msg_control;
- insn->bits3.dp_render_cache.pixel_scoreboard_clear = 0;
- insn->bits3.dp_render_cache.msg_type = msg_type;
- insn->bits3.dp_render_cache.send_commit_msg = 0;
- insn->bits3.dp_render_cache.header_present = 1;
- insn->bits3.dp_render_cache.response_length = response_length;
- insn->bits3.dp_render_cache.msg_length = msg_length;
- insn->bits3.dp_render_cache.end_of_thread = 0;
+ insn->bits3.gen6_dp.binding_table_index = binding_table_index;
+ insn->bits3.gen6_dp.msg_control = msg_control;
+ insn->bits3.gen6_dp.pixel_scoreboard_clear = 0;
+ insn->bits3.gen6_dp.msg_type = msg_type;
+ insn->bits3.gen6_dp.send_commit_msg = 0;
+ insn->bits3.gen6_dp.header_present = 1;
+ insn->bits3.gen6_dp.response_length = response_length;
+ insn->bits3.gen6_dp.msg_length = msg_length;
+ insn->bits3.gen6_dp.end_of_thread = 0;
insn->header.destreg__conditionalmod = target_function;
} else if (intel->gen == 5) {
insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri/i965/brw_structs.h
index 8d4797fb..6132bb9 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1704,7 +1704,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
- } dp_render_cache;
+ } gen6_dp;
struct {
GLuint function_control:16;
--
1.7.4.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
